39.8.18 Synchronization Busy

Name: SYNCBUSY
Offset: 0x20
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     ANACTRLSWTRIGSHIFTCORRGAINCORR 
Access RRRR 
Reset 0000 
Bit 76543210 
 OFFSETCORRWINUTWINLTWINCTRLMUXCTRLCTRLCENABLESWRST 
Access RRRRRRRR 
Reset 00000000 

Bit 11 – ANACTRL Analog Control Synchronization Busy

This bit is cleared when the synchronization of ANACTRL register between the clock domains is complete.

This bit is set when the synchronization of ANACTRL register between clock domains is started.

Bit 10 – SWTRIG Software Trigger Synchronization Busy

This bit is cleared when the synchronization of SWTRIG register between the clock domains is complete.

This bit is set when the synchronization of SWTRIG register between clock domains is started.

Bit 9 – SHIFTCORR Shift Correction Synchronization Busy

This bit is cleared when the synchronization of SHIFTCORR register between the clock domains is complete.

This bit is set when the synchronization of SHIFTCORR register between clock domains is started.

Bit 8 – GAINCORR Gain Correction Synchronization Busy

This bit is cleared when the synchronization of GAINCORR register between the clock domains is complete.

This bit is set when the synchronization of GAINCORR register between clock domains is started.

Bit 7 – OFFSETCORR Offset Correction Synchronization Busy

This bit is cleared when the synchronization of OFFSETCORR register between the clock domains is complete.

This bit is set when the synchronization of OFFSETCORR register between clock domains is started.

Bit 6 – WINUT Window Monitor Lower Threshold Synchronization Busy

This bit is cleared when the synchronization of WINUT register between the clock domains is complete.

This bit is set when the synchronization of WINUT register between clock domains is started.

Bit 5 – WINLT Window Monitor Upper Threshold Synchronization Busy

This bit is cleared when the synchronization of WINLT register between the clock domains is complete.

This bit is set when the synchronization of WINLT register between clock domains is started.

Bit 4 – WINCTRL Window Monitor Control Synchronization Busy

This bit is cleared when the synchronization of WINCTRL register between the clock domains is complete.

This bit is set when the synchronization of WINCTRL register between clock domains is started.

Bit 3 – MUXCTRL Mux Control Synchronization Busy

This bit is cleared when the synchronization of MUXCTRL register between the clock domains is complete.

This bit is set when the synchronization of MUXCTRL register between clock domains is started.

Bit 2 – CTRLC Control C Synchronization Busy

This bit is cleared when the synchronization of CTRLC register between the clock domains is complete.

This bit is set when the synchronization of CTRLC register between clock domains is started.

Bit 1 – ENABLE ENABLE Synchronization Busy

This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.

This bit is set when the synchronization of ENABLE register between clock domains is started.

Bit 0 – SWRST SWRST Synchronization Busy

This bit is cleared when the synchronization of SWRST register between the clock domains is complete.

This bit is set when the synchronization of SWRST register between clock domains is started