39.8.3 Control B

Name: CTRLB
Offset: 0x02
Reset: 0x2000
Property: PAC Write-Protection, Enable-Protected

Bit 15141312111098 
 SKPCNT[3:0] OSR[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0010000 
Bit 76543210 
 PRESCALER[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:12 – SKPCNT[3:0] Skip Count

How many skip samples before retrieve the first valid sample.

The first valid sample starts from the third sample onward.

Bits 10:8 – OSR[2:0] Over Sampling Ratio

OSR is the Over Sampling Ratio which can be modified to change the output data rate.

The OSR must never be changed while the SDADC is running. One must first place the SDADC in reset state, modify the OSR and then run the SDADC again.

Example: The sampling rate of the SDADC is 1.5Msps/OSR. The maximum sampling rate is then 1.5MSPS/OSR64 ≅ 23.4ksps and the minimum sampling rate is 1.5Msps/OSR1024 ≅ 1.5ksps

ValueNameDescription
0x0 OSR64 Over Sampling Ratio is 64
x01 OSR128 Over Sampling Ratio is 128
0x2 OSR256 Over Sampling Ratio is 256
0x3 OSR512 Over Sampling Ratio is 512
0x4 OSR1024 Over Sampling Ratio is 1024
0x4 - 0xF - Reserved

Bits 7:0 – PRESCALER[7:0] Prescaler Configuration

The ADC uses the SDADC Clock to perform conversions.

The CLK_SDADC_PRESCAL clock range is between CLK_GEN_SDADC/2, if PRESCAL is 0, and CLK_GEN_SDADC/512, if PRESCAL is set to 255 (0xFF). PRESCAL must be programmed in order to provide an CLK_SDADC_PRESCAL clock frequency according to the parameters given in the product Electrical Characteristics section.