36.6.9 Status
| Name: | STATUS |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WINSTATE0[1:0] | COMPSTATE1 | COMPSTATE0 | |||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 4:5 – WINSTATEn[1:0] Window n State
This bit field indicates the current state of the input signal if Window n mode is enabled.
| Value | Name | Description |
|---|---|---|
| 0x0 | ABOVE | The input signal is above window n |
| 0x1 | INSIDE | The input signal is inside window n |
| 0x2 | BELOW | The input signal is below window n |
| Other | — | Reserved |
Bits 0, 1 – COMPSTATEn Comparator n State
This bit is cleared when the positive input voltage is lower than or equal to the negative input voltage.
This bit is set when the positive input voltage is higher than the negative input voltage.
| Value | Description |
|---|---|
| 0 | The COMPn-OUT signal is low |
| 1 | The COMPn-OUT signal is high |