17.6.7 Peripheral Interrupt Flag Status and Clear B
| Name: | INTFLAGB |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HMATRIXHS | MTB | DMAC | NVMCTRL | DSU | PORT | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – HMATRIXHS HMATRIXHS Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 4 – MTB MTB Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 3 – DMAC DMAC Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 2 – NVMCTRL NVMCTRL Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 1 – DSU DSU Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.
Bit 0 – PORT PORT Peripheral Interrupt Flag
A flag is cleared by writing a ‘1’ to it.
A flag is set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGB bit, and will generate an interrupt request
if Interrupt Enable Set (INTENSET.ERR) bit or Interrupt Enable Clear (INTENCLR.ERR)
bit is ‘1’.
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will clear the corresponding interrupt
flag.