17.6.3 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
        ERR 
Access R/W 
Reset 0 

Bit 0 – ERR Peripheral Access Error Interrupt Disable

This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the Interrupt Flag register (INTFLAGAHB, INTFLAGx) bits is set.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Peripheral Access Error interrupt Enable bit, which disables the Peripheral Access Error interrupt.

ValueDescription
0 The Peripheral Access Error interrupt is enabled
1 The Peripheral Access Error interrupt is disabled