17.6.1 Write Control

Name: WRCTRL
Offset: 0x00
Reset: 0x00000000
Property: –

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 KEY[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PERID[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PERID[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:16 – KEY[7:0] Peripheral Access Control Key

This field defines the peripheral access control key.

ValueNameDescription
0x0 OFF No action
0x1 CLR Clear the peripheral write-control
0x2 SET Set the peripheral write-control
0x3 SETLCK Set and lock the peripheral write-control until the next hardware reset

Bits 15:0 – PERID[15:0] Peripheral Identifier

This field represents the peripheral whose access control is changed using WRCTRL.KEY.

ValueNameDescription
0x00 PAC APBA peripheral
0x01 PM APBA peripheral
0x02 MCLK APBA peripheral
0x03 RSTC APBA peripheral
0x04 OSCCTRL APBA peripheral
0x05 OSC32KCTRL APBA peripheral
0x06 SUPC APBA peripheral
0x07 GCLK APBA peripheral
0x08 WDT APBA peripheral
0x09 RTC APBA peripheral
0x0A EIC APBA peripheral
0x20 PORT APBB peripheral
Note:
  1. IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.
  2. PORT read/write attempts on non-implemented registers, including addresses beyond the last implemented register group do not generate a PAC protection error.
0x21 DSU APBB peripheral
0x22 NVMCTRL APBB peripheral
0x23 DMAC APBB peripheral
0x24 MTB APBB peripheral
0x25 HMATRIXHS APBB peripheral
0x40 EVSYS APBC peripheral
0x41 SERCOM0 APBC peripheral
0x42 SERCOM1 APBC peripheral
0x43 TC0 APBC peripheral
0x44 TC1 APBC peripheral
0x45 TC2 APBC peripheral
0x46 TCC0 APBC peripheral
0x47 ADC0 APBC peripheral
0x48 AC APBC peripheral
0x49 CCL APBC peripheral
0x4A PTC APBC peripheral
0x4B SYSCTRL APBC peripheral
Other — Reserved