37.4 Power Supply

Table 37-5. Power Supply DC Electrical Specifications
Standard operating conditions: V_DDIO = AVDD = 1.8V to 5.5V (Unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_5	V_{DD_CIN}⁽³⁾	V_DD Input bypass parallel capacitor pair	—	0.1	—	µF	Bulk ceramic or solid tantalum capacitor with ESR < 0.5Ω
	V_{DD_CIN}⁽³⁾	V_DD Input bypass parallel capacitor pair	—	10	—	nF	Ceramic X7R capacitor with ESR < 0.5Ω on all V_DDIO2 pins
	V_{DDIO2_CIN}⁽³⁾	V_DDIO2 Input bypass parallel capacitor pair	—	0.1	—	µF	Bulk ceramic or solid tantalum capacitor with ESR < 0.5Ω
	V_{DDIO2_CIN}⁽³⁾	V_DDIO2 Input bypass parallel capacitor pair	—	10	—	nF	Ceramic X7R capacitor with ESR < 0.5Ω on all V_DDIO2 pins
REG_9	V_{REFA_CIN}⁽³⁾	External V_REFA Input bypass parallel capacitor pair	—	0.1	—	µF	Bulk ceramic or solid tantalum capacitor with ESR < 0.5Ω
REG_9	V_{REFA_CIN}⁽³⁾	External V_REFA Input bypass parallel capacitor pair	—	10	—	nF	Ceramic X7R capacitor with ESR < 0.5Ω
REG_17	AVDD_CIN⁽³⁾	AVDD Input bypass parallel capacitor pair	—	0.1	—	µF	Bulk Ceramic or solid tantalum capacitor with ESR < 0.5Ω
REG_17	AVDD_CIN⁽³⁾	AVDD Input bypass parallel capacitor pair	—	10	—	nF	Ceramic X7R capacitor with ESR < 0.5Ω
REG_23	AVDD_LEXT⁽¹⁾	AVDD series ferrite bead DC resistance (DCR)	—	—	0.1	Ω	≥ 600Ω @ 100 MHz
REG_25	AVDD_LEXT⁽¹⁾	Ferrite bead current rating	500	—	—	mA	—
REG_37	V_DD⁽²⁾	V_DD input voltage range	1.8	—	5.5	V	—
REG_37A	V_DDIO2	V_DDIO2 input voltage range	1.6	—	5.5	V	—
REG_39	AVDD⁽²⁾	AVDD input voltage range	1.8	—	5.5	V	—
REG_40	V_DDCORE⁽⁴⁾	Core voltage	—	2.0	—	V	With AVDD = V_DD > 2.4V
REG_43A	S_{VDD_R}	V_DD rise ramp rate required to ensure the internal Power-On Reset signal	—	—	0.05	V/ms	With BOD disabled, failure to meet this specification may lead to start-up issues or unexpected behaviors
REG_43A	S_{VDD_R}	V_DD change rate required to prevent the internal Power-On Reset signal during operation	—	—	1.2	V/µs	1.8V ≤ V_DD ≤ 5.5V
REG_43B	S_{VDDIO2_R}	V_DDIO2 rise ramp rate required to ensure the internal Power-On Reset signal	—	—	0.05	V/ms	—
REG_45	V_POR	Power-On Reset	—	1.6	—	V	V_DD power- up or power-down (see Parameter REG_43, V_DD ramp rate)
REG_47	V_DD / V_DDIO2 / AVDD BOR	V_DD / V_DDIO2 / AVDD Brown-Out Reset thresholds	1.8	1.9	2.1	V	BODLEVEL0
			2.3	2.45	2.6	V	BODLEVEL1
			2.55	2.7	2.85	V	BODLEVEL2
			2.7	2.85	3.0	V	BODLEVEL3
Note: Ferrite Bead I_SAT(min) ≥ (I_DDANA(max) x 1.15). V_DD and AVDD must be at the same voltage level. All bypass capacitors should be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU. For V_DD < 2.4 V_DDCORE can be lower than V_DD.