29.6.7 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Error
Interrupt Enable bit, which disables the Error interrupt.
| Value | Description |
|---|---|
| 0 | Error interrupt is disabled |
| 1 | Error interrupt is enabled |
Bit 5 – RXBRK Receive Break Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Receive
Break Interrupt Enable bit, which disables the Receive Break interrupt.
| Value | Description |
|---|---|
| 0 | Receive Break interrupt is disabled |
| 1 | Receive Break interrupt is enabled |
Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Clear To
Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change
interrupt.
| Value | Description |
|---|---|
| 0 | Clear To Send Input Change interrupt is disabled |
| 1 | Clear To Send Input Change interrupt is enabled |
Bit 3 – RXS Receive Start Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Receive
Start Interrupt Enable bit, which disables the Receive Start interrupt.
| Value | Description |
|---|---|
| 0 | Receive Start interrupt is disabled |
| 1 | Receive Start interrupt is enabled |
Bit 2 – RXC Receive Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Receive
Complete Interrupt Enable bit, which disables the Receive Complete interrupt.
| Value | Description |
|---|---|
| 0 | Receive Complete interrupt is disabled |
| 1 | Receive Complete interrupt is enabled |
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Transmit
Complete Interrupt Enable bit, which disables the Transmit Complete interrupt.
| Value | Description |
|---|---|
| 0 | Transmit Complete interrupt is disabled |
| 1 | Transmit Complete interrupt is enabled |
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit will clear the Data
Register Empty Interrupt Enable bit, which disables the Data Register Empty
interrupt.
| Value | Description |
|---|---|
| 0 | Data Register Empty interrupt is disabled |
| 1 | Data Register Empty interrupt is enabled |