29.6.4 Baud - Arithmetic Mode
This register description is valid only in Arithmetic Baud Rate Generation mode
(CTRLA.SAMPR[0]=0).
| Name: | BAUD |
| Offset: | 0x0C |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BAUD[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BAUD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – BAUD[15:0] Baud Value
These bits control the clock generation, as described in the Clock Generation – Baud-Rate Generator section.