29.6.1 Control A

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized


Bit	31	30	29	28	27	26	25	24
		DORD	CPOL	CMODE	FORM[3:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SAMPA[1:0]		RXPO[1:0]				TXPO[1:0]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	15	14	13	12	11	10	9	8
	SAMPR[2:0]							IBON
Access	R/W	R/W	R/W					R/W
Reset	0	0	0					0


Bit	7	6	5	4	3	2	1	0
	RUNSTDBY			MODE[2:0]			ENABLE	SWRST
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the Data register.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	MSB	MSb is transferred first
1	LSB	LSb is transferred first

Bit 29 – CPOL Clock Polarity

This bit selects the relationship between data output change and data input sampling in Synchronous mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	IDLE_LOW	TxD Change: Rising XCK edge, RxD Sample: Falling XCK edge
1	IDLE_HIGH	TxD Change: Falling XCK edge, RxD Sample: Rising XCK edge

Bit 28 – CMODE Communication Mode

This bit selects asynchronous or synchronous communication.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	ASYNC	Asynchronous communication
1	SYNC	Synchronous communication

Bits 27:24 – FORM[3:0] Frame Format

These bits define the frame format.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	USART_FRAME_NO_PARITY	USART frame
0x1	USART_FRAME_WITH_PARITY	USART frame with parity
0x2	USART_FRAME_LINBRKGEN	LIN Host - Break and sync generation. See LIN Command (CTRLB.LINCMD).
0x4	USART_FRAME_AUTO_BAUD_NO_PARITY	Auto-baud (LIN Client) - break detection and auto-baud
0x5	USART_FRAME_AUTO_BAUD_WITH_PARITY	Auto-baud - break detection and auto-baud with parity

Bits 23:22 – SAMPA[1:0] Sample Adjustment

These bits define the sample adjustment.

Note:

This bit field is enable-protected. This bit field is not synchronized.
This adjustment depends on the over-sampling setting 16x (CTRLA.SAMPR = 0 or 1) or 8x (CTRLA.SAMPR = 2 or 3)

Value	Name	Description
0x0	ADJ0	16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5
0x1	ADJ1	16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6
0x2	ADJ2	16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7
0x3	ADJ3	16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8

Bits 21:20 – RXPO[1:0] Receive Data Pinout

These bits define the receive data (RxD) pin configuration.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	MUX0	SERCOM PAD[0] is used for data reception
0x1	MUX1	SERCOM PAD[1] is used for data reception
0x2	MUX2	SERCOM PAD[2] is used for data reception
0x3	MUX3	SERCOM PAD[3] is used for data reception

Bits 17:16 – TXPO[1:0] Transmit Data Pinout

These bits define the transmit data (TxD) and XCK pin configurations.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	MUX0	PAD[0]=TxD, PAD[1]=XCK
0x1	MUX1	PAD[2]=TxD, PAD[3]=XCK
0x2	MUX2	PAD[0]=TxD, PAD[2]=RTS/TE, PAD[3]=CTS
0x3	MUX3	PAD[0]=TxD, PAD[1]=XCK, PAD[2]=RTS/TE

Bits 15:13 – SAMPR[2:0] Sample Rate

These bits select the sample rate.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	16X_ARITHMETIC	16x over-sampling using arithmetic baud rate generation
0x1	16X_FRACTIONAL	16x over-sampling using fractional baud rate generation
0x2	8X_ARITHMETIC	8x over-sampling using arithmetic baud rate generation
0x3	8X_FRACTIONAL	8x over-sampling using fractional baud rate generation
0x4	3X_ARITHMETIC	3x over-sampling using arithmetic baud rate generation

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	STATUS.BUFOVF is asserted when a buffer overflow occurs in the data stream
1	STATUS.BUFOVF is asserted immediately upon buffer overflow

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in Standby sleep mode. Refer to Sleep Mode Operation for more information.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The USART does not operate in Standby sleep mode
1	The USART operates in Standby sleep mode

Bits 4:2 – MODE[2:0] Operating Mode

This bit field controls the SERCOM mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	USART_EXT	USART with external clock
0x1	USART_INT	USART with internal clock
0x2	SPI_SLAVE	SPI Client mode
0x3	SPI_MASTER	SPI Host mode
0x4	I2C_SLAVE	I²C Client mode
0x5	I2C_MASTER	I²C Host mode

Bit 1 – ENABLE Enable

Note:

This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
This bit is not enable-protected.

Value	Description
0	The peripheral is disabled or being disabled
1	The peripheral is enabled or being enabled

Bit 0 – SWRST Software Reset

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing ‘1’ to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Note:

This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST synchronization is complete.
This bit is not enable-protected.

Value	Description
0	There is no reset operation in progress
1	The reset operation is in progress