29.6.3 Control C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					HDRDLY[1:0]		BRKLEN[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
						GTIME[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0

Bits 11:10 – HDRDLY[1:0] LIN Host Header Delay

These bits define the delay between break and sync transmission in addition to the delay between the sync and identifier (ID) fields when in LIN Host mode (CTRLA.FORM = USART_FRAME_LINBRKGEN).

This field is only valid when using the LIN header command (CTRLB.LINCMD = AUTO_TRANSMIT_CMD).

Value	Name	Description
0x0	1_BIT_TIME	Delay between break and sync transmission is one bit time. Delay between sync and ID transmission is one bit time.
0x1	4_BIT_TIME	Delay between break and sync transmission is four bit times. Delay between sync and ID transmission is four bit times.
0x2	8_BIT_TIME	Delay between break and sync transmission is eight bit times. Delay between sync and ID transmission is four bit times.
0x3	14_BIT_TIME	Delay between break and sync transmission is 14 bit times. Delay between sync and ID transmission is four bit times.

Bits 9:8 – BRKLEN[1:0] LIN Host Break Length

These bits define the length of the break field transmitted when in LIN Host mode (CTRLA.FORM = USART_FRAME_LINBRKGEN).

Value	Name	Description
0x0	13_BIT_TIME	The break field transmission is 13 bit times
0x1	17_BIT_TIME	The break field transmission is 17 bit times
0x2	21_BIT_TIME	The break field transmission is 21 bit times
0x3	26_BIT_TIME	The break field transmission is 26 bit times

Bits 2:0 – GTIME[2:0] Guard Time

These bits define the guard time when using RS485 mode.

For RS485 mode, the guard time is programmable from 0–7 bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.

Name:	CTRLC
Offset:	0x08
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected