25.6.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CKSEL | ENABLE | SWRST | |||||||
| Access | R/W | R/W | W | ||||||
| Reset | 0 | 0 | 0 |
Bit 4 – CKSEL Clock Selection
The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 kHz is required for filtering) or by CLK_OSC32K (when power consumption is the priority).
Note: Any writes to this bit while
synchronization of CTRLA.ENABLE or CTRLA.SWRST is ongoing, or the CTRLA.ENABLE bit is
‘
1’, will cause a peripheral bus error. However, this bit itself
is not synchronized. | Value | Name | Description |
|---|---|---|
| 0 | GCLK_EIC | The EIC is clocked by GCLK_EIC |
| 1 | CLK_OSC32K | The EIC is clocked by CLK_OSC32K |
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized:
SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is
complete. Any writes to this bit while synchronization is ongoing will cause a
peripheral bus error.
| Value | Description |
|---|---|
| 0 | The EIC is disabled |
| 1 | The EIC is enabled |
Bit 0 – SWRST Software Reset
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit resets all registers in the EIC
to their initial state, and the EIC will be disabled.
Writing a ‘1’ to this bit will always take precedence,
meaning that all other writes in the same write operation will be discarded.
Note: This bit is write-synchronized:
SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST synchronization is complete.
Any register writes while CTRLA.SWRST is ‘
1’ will cause a peripheral
bus error.| Value | Description |
|---|---|
| 0 | There is no ongoing reset operation |
| 1 | The reset operation is ongoing |