Flash Multi-page Erase Mode
The Multi-page Erase mode (FLMPERn) causes each write to the memory array to erase multiple pages. This mode can be configured to erase 2, 4, 8, 16 or 32 pages with a single write.
The LSbs of the page address is ignored when determining which Flash pages are erased. This means that, for a 4-page erase, providing an address to a word within page 8 to 11 will cause all pages 8-11 to be erased.
| CMD | Pages Erased | Description |
|---|---|---|
| FLMPER2 | 2 | Pages matching FPAGE[N:1] are erased. The value in FPAGE[0] is ignored. |
| FLMPER4 | 4 | Pages matching FPAGE[N:2] are erased. The value in FPAGE[1:0] is ignored. |
| FLMPER8 | 8 | Pages matching FPAGE[N:3] are erased. The value in FPAGE[2:0] is ignored. |
| FLMPER16 | 16 | Pages matching FPAGE[N:4] are erased. The value in FPAGE[3:0] is ignored. |
| FLMPER32 | 32 | Pages matching FPAGE[N:5] are erased. The value in FPAGE[4:0] is ignored. |
Note: FPAGE is the page number when doing a Flash erase. Refer to the Memory Access section for details. Note: “N” refers to the MSb of the FPAGE, i.e.: [N:1] refers to all bits in FPAGE except the LSb. | ||
All pages that are erased at once must be within a single logical NVM section; Boot or application code. If the number of pages selected crosses the boundary between two sections, the operation is aborted and STATUS.LOCKE is set.
If the rows reside in a region that is locked (either through BOOTPROT and/or LOCK bits), the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.