29.1 Device-Specific Information

Table 29-1. CLC Summary Table
CLC Module InstancesInputs per InstanceCLC OutputsPeripheral Bus Speed
1084Slow
Table 29-2. DS1 Data Selection MUX 1 Signal Selection bits
Value (binary)Description
111Virtual Pin 9 Output
110Virtual Pin 8 Output
101CLCINB
100CLCINA
011CLC2 Output
010CLC1 Output
001CLKGEN14
000Standard Peripheral Clock (system clock/2)
Table 29-3. DS2 Data Selection MUX 2 Signal Selection bits
Value (binary)Description
111Virtual Pin 11 Output
110Virtual Pin 10 Output
101CLCINE
100CLCIND
011CLCINC
010CLC4 Output
001CLC3 Output
000Slow Peripheral Clock (system clock/4)
Table 29-4. DS3 Data Selection MUX 3 Signal Selection bits
Value (binary)Description
111Virtual Pin 13 Output
110Virtual Pin 12 Output
101CLCING
100CLCINF
011CLC7 Output
010CLC6 Output
001CLC5 Output
000BFRC/244
Table 29-5. DS4 Data Selection MUX 4 Signal Selection bits
Value (binary)Description
111Virtual Pin 15 Output
110Virtual Pin 14 Output
101CLCINJ
100CLCINI
011CLCINH
010CLC9 Output
001CLC8 Output
000FRC