17.1 Device-Specific Information

Table 17-1. ADC Summary Table
Number of Cores	Max Number of Channels	Max Input Clock	Clock Source	Peripheral Bus Speed
5	16	See Electrical Characteristics (ADC)	CLKGEN6	Fast

The number of available positive and negative analog inputs is dependent on package size, as shown in the ADC External Input Availability table.

Table 17-2. ADC Input Availability
ADC Input	48-Pin	64-Pin	80-Pin	100-Pin	128-Pin	129-Pin	Comments
AD1ANN0	AV_SS						ADC 1 ground negative input 0 supporting Differential mode
AD1ANN1		x	x	x	x	x	ADC 1 negative input 1 supporting Differential mode
AD1ANN2	x	x	x	x	x	x	ADC 1 negative input 2 supporting Differential mode
AD1ANN3	Reserved						Reserved
AD1AN0	x	x	x	x	x	x	ADC 1 positive input 0
AD1AN1	x	x	x	x	x	x	ADC 1 positive input 1
AD1AN2	x	x	x	x	x	x	ADC 1 positive input 2
AD1AN3	x	x	x	x	x	x	ADC 1 positive input 3
AD1AN4		x	x	x	x	x	ADC 1 positive input 4
AD1AN5	Reserved						Reserved
AD1AN6	Internal						ADC 1 15/16*V_DD reference input
AD1AN7	Internal						ADC 1 UREF input
AD2ANN0	AV_SS						ADC 2 ground negative input 0 supporting Differential mode
AD2ANN1			x	x	x	x	ADC 2 negative input 1 supporting Differential mode
AD2ANN2	x	x	x	x	x	x	ADC 2 negative input 2 supporting Differential mode
AD2ANN3	Reserved						Reserved
AD2AN0	x	x	x	x	x	x	ADC 2 positive input 0
AD2AN1	x	x	x	x	x	x	ADC 2 positive input 1
AD2AN2	x	x	x	x	x	x	ADC 2 positive input 2
AD2AN3		x	x	x	x	x	ADC 2 positive input 3
AD2AN4		x	x	x	x	x	ADC 2 positive input 4
AD2AN5			x	x	x	x	ADC 2 positive input 5
AD2AN6	Internal						ADC 2 15/16*V_DD reference input
AD2AN7	Internal						ADC 2 UREF input
AD3ANN0	AV_SS						ADC 3 ground negative input 0 supporting Differential mode
AD3ANN1			x	x	x	x	ADC 3 negative input 1 supporting Differential mode
AD3ANN2	x	x	x	x	x	x	ADC 3 negative input 2 supporting Differential mode
AD3ANN3	Reserved						Reserved
AD3AN0	x	x	x	x	x	x	ADC 3 positive input 0
AD3AN1	x	x	x	x	x	x	ADC 3 positive input 1
AD3AN2	x	x	x	x	x	x	ADC 3 positive input 2
AD3AN3			x	x	x	x	ADC 3 positive input 3
AD3AN4		x	x	x	x	x	ADC 3 positive input 4
AD3AN5	x	x	x	x	x	x	ADC 3 positive input 5
AD3AN6	Internal						ADC 3 15/16*AV_DD reference input
AD3AN7	Internal						ADC 3 UREF input
AD4ANN0	AV_SS						ADC 4 ground negative input 0 supporting Differential mode
AD4ANN1	x	x	x	x	x	x	ADC 4 negative input 1 supporting Differential mode
AD4ANN2	x	x	x	x	x	x	ADC 4 negative input 2 supporting Differential mode
AD4ANN3	Reserved						Reserved
AD4AN0	x	x	x	x	x	x	ADC 4 positive input 0
AD4AN1	x	x	x	x	x	x	ADC 4 positive input 1
AD4AN2	x	x	x	x	x	x	ADC 4 positive input 2
AD4AN3	x	x	x	x	x	x	ADC 4 positive input 3
AD4AN4		x	x	x	x	x	ADC 4 positive input 4
AD4AN5	x	x	x	x	x	x	ADC 4 positive input 5
AD4AN6	Internal						ADC 4 15/16*AV_DD reference input
AD4AN7	Internal						ADC 4 UREF input
AD5ANN0	AV_SS						ADC 5 ground negative input 0 supporting Differential mode
AD5ANN1	x	x	x	x	x	x	ADC 5 negative input 1 supporting Differential mode
AD5ANN2		x	x	x	x	x	ADC 5 negative input 2 supporting Differential mode
AD5ANN3	Reserved						Reserved
AD5AN0	x	x	x	x	x	x	ADC 5 positive input 0
AD5AN1	x	x	x	x	x	x	ADC 5 positive input 1
AD5AN2		x	x	x	x	x	ADC 5 positive input 2
AD5AN3	x	x	x	x	x	x	ADC 5 positive input 3
AD5AN4	x	x	x	x	x	x	ADC 5 positive input 4
AD5AN5	Internal						ADC 5 Touch ADC input
AD5AN6	Internal						ADC 5 15/16*AV_DD reference input
AD5AN7	Internal						ADC 5 UREF input
AD5AN8	Internal						ADC 5 VDDCORE input

Table 17-3. TRG1SRC Trigger Source Selection Bits
Value	Description
`111111-101000`	Reserved
`100111`	SCCP8 OCMP/ICAP out
`100110`	SCCP7 OCMP/ICAP out
`100101`	SCCP6 OCMP/ICAP out
`100100`	SCCP5 OCMP/ICAP out
`100011`	SCCP4 OCMP/ICAP out
`100010`	SCCP3 OCMP/ICAP out
`100001`	SCCP2 OCMP/ICAP out
`100000`	SCCP1 OCMP/ICAP out
`011111`	ADTRG31 (PPS)
`011110`	PTG trigger 12
`011101`	MCCP9 OCMP/ICAP out
`011100`	CLC4 out
`011011`	CLC3 out
`011010`	ITC
`011001`	APWM 4 ADC trigger 1
`011000`	APWM 3 ADC trigger 1
`010111`	APWM 2 ADC trigger 2
`010110`	APWM 2 ADC trigger 1
`010101`	APWM 1 ADC trigger 2
`010100`	APWM 1 ADC trigger 1
`010011`	PWM 8 ADC trigger 2
`010010`	PWM 8 ADC trigger 1
`010001`	PWM 7 ADC trigger 2
`010000`	PWM 7 ADC trigger 1
`001111`	PWM 6 ADC trigger 2
`001110`	PWM 6 ADC trigger 1
`001101`	PWM 5 ADC trigger 2
`001100`	PWM 5 ADC trigger 1
`001011`	PWM 4 ADC trigger 2
`001010`	PWM 4 ADC trigger 1
`001001`	PWM 3 ADC trigger 2
`001000`	PWM 3 ADC trigger 1
`000111`	PWM 2 ADC trigger 2
`000110`	PWM 2 ADC trigger 1
`000101`	PWM 1 ADC trigger 2
`000100`	PWM 1 ADC trigger 1
`000011-000010`	Reserved
`000001`	Software trigger initiated by using the ADnSWTRG register.
`000000`	Triggers are disabled.

Table 17-4. TRG2SRC Trigger Source Selection Bits
Value	Description
`111111-101000`	Reserved
`100111`	SCCP8 OCMP/ICAP out
`100110`	SCCP7 OCMP/ICAP out
`100101`	SCCP6 OCMP/ICAP out
`100100`	SCCP5 OCMP/ICAP out
`100011`	SCCP4 OCMP/ICAP out
`100010`	SCCP3 OCMP/ICAP out
`100001`	SCCP2 OCMP/ICAP out
`100000`	SCCP1 OCMP/ICAP out
`011111`	ADTRG31 (PPS)
`011110`	PTG trigger 12
`011101`	MCCP9 OCMP/ICAP out
`011100`	CLC4 out
`011011`	CLC3 out
`011010`	ITC
`011001`	APWM 4 ADC trigger 1
`011000`	APWM 3 ADC trigger 1
`010111`	APWM 2 ADC trigger 2
`010110`	APWM 2 ADC trigger 1
`010101`	APWM 1 ADC trigger 2
`010100`	APWM 1 ADC trigger 1
`010011`	PWM 8 ADC trigger 2
`010010`	PWM 8 ADC trigger 1
`010001`	PWM 7 ADC trigger 2
`010000`	PWM 7 ADC trigger 1
`001111`	PWM 6 ADC trigger 2
`001110`	PWM 6 ADC trigger 1
`001101`	PWM 5 ADC trigger 2
`001100`	PWM 5 ADC trigger 1
`001011`	PWM 4 ADC trigger 2
`001010`	PWM 4 ADC trigger 1
`001001`	PWM 3 ADC trigger 2
`001000`	PWM 3 ADC trigger 1
`000111`	PWM 2 ADC trigger 2
`000110`	PWM 2 ADC trigger 1
`000101`	PWM 1 ADC trigger 2
`000100`	PWM 1 ADC trigger 1
`000011`	Conversion repeat timer trigger defined by RPTCNT[5:0] (ADnCON[23:18]) bits.
`000010`	Immediate re-trigger request
`000001`	Software trigger initiated by using the ADnSWTRG register.
`000000`	Triggers are disabled.