20.1 Device-Specific Information

Table 20-1. DAC Summary
DAC Module Instances	Inputs per Instance	DAC Outputs	Clock Source	Peripheral Bus Speed
8	5 External, 1 Internal	2	CLKGEN7	Standard

Table 20-2. High-Speed Analog Comparator Module Availability
Comparator Input	48-Pin	64-Pin	80-Pin	100-Pin	128-Pin	129-Pin	PPS
CMPNC	x	x	x	x	x	x	No
CMPND	x	x	x	x	x	x	No
CMPNE	—	x	x	x	x	x	No
CMPNF	—	x	x	x	x	x	No
CMPP	x	x	x	x	x	x	No
CMP1A	x	x	x	x	x	x	No
CMP1B	x	x	x	x	x	x	No
CMP1C	x	x	x	x	x	x	No
CMP1D	—	—	x	x	x	x	No
CMP2A	x	x	x	x	x	x	No
CMP2B	x	x	x	x	x	x	No
CMP2C	x	x	x	x	x	x	No
CMP2D	-	x	x	x	x	x	No
CMP3A	x	x	x	x	x	x	No
CMP3B	x	x	x	x	x	x	No
CMP3C	x	x	x	x	x	x	No
CMP3D	—	—	x	x	x	x	No
CMP4A	x	x	x	x	x	x	No
CMP4B	x	x	x	x	x	x	No
CMP4C	x	x	x	x	x	x	No
CMP4D	x	x	x	x	x	x	No
CMP5A	x	x	x	x	x	x	No
CMP5B	x	x	x	x	x	x	No
CMP5C	—	x	x	x	x	x	No
CMP5D	—	—	x	x	x	x	No
CMP6A	x	x	x	x	x	x	No
CMP6B	x	x	x	x	x	x	No
CMP6C	-	x	x	x	x	x	No
CMP7A	x	x	x	x	x	x	No
CMP7B	—	x	x	x	x	x	No
CMP7C	—	—	—	x	x	x	No
CMP7D	x	x	x	x	x	x	No
CMP8A	—	x	x	x	x	x	No
CMP8B	—	—	x	x	x	x	No
CMP8C	—	—	—	x	x	x	No
CMP8D	—	x	x	x	x	x	No

Table 20-3. Slope Start Signal Selection (SLPSTRT)
Slope Start Signal Selection	Source
15	N/A
14	RPV 15
13	RPV 14
12	APWM4
11	APWM3
10	APWM2
9	APWM1
8	PWM8
7	PWM7
6	PWM6
5	PWM5
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 20-4. Slope Stop A Signal Select bits (SLPSTOPA)
Slope Stop A Signal Selection	Source
15	N/A
14	RPV 15
13	RPV 14
12	APWM4
11	APWM3
10	APWM2
9	APWM1
8	PWM8
7	PWM7
6	PWM6
5	PWM5
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 20-5. Slope Stop B Signal Select bits (SLPSTOPB)
Slope Stop B Signal Selection	Source
15	N/A
14	RPV 15
13	RPV 14
12	APWM4
11	APWM3
10	APWM2
9	APWM1
8	PWM8
7	PWM7
6	PWM6
5	PWM5
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 20-6. Hysteretic Comparator Function Input Select Bits (HCFSEL)
Hysterectic Comparator Function Input Selection	Description
15	N/A
14	RPV 15
13	RPV 14
12	APWM4H
11	APWM3H
10	APWM2H
9	APWM1H
8	PWM8H
7	PWM7H
6	PWM6H
5	PWM5H
4	PWM4H
3	PWM3H
2	PWM2H
1	PWM1H
0	N/A

The calibration register FPDMDAC is located in Flash at 0x7F20E0 with the POSINLADJ, NEGINLADJ and DNLADJ bit fields. The location should be copied and written to the corresponding bit fields in the DACCTRL1 SFR at start up.

Table 20-7. FPDMDAC Calibration Register
Name	Address Offset	Bit Field	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3
FPDMDAC	0x000	31:24	—	—	—	—	cfg_dac_filter[3:0]
		23:16	—	—	POSINLADJ[5:0]
		15:8	—	NEGINLADJ[6:0]
		7:0	—	—	—	DNLADJ[4:0]