28.3 Architectural Overview

Select dsPIC33A family devices include one or more Capture/Compare/PWM/Timer (CCP) modules. The multipurpose timer module provides the functionality of the comparable Input Capture, Output Compare and General Purpose Timer peripherals found in all other devices.

CCP modules can operate in one of three major modes:
  • Time Base – The module generates internal signals, triggers and interrupt events only based on a 16-bit or 32-bit count value. All associated I/O functions are disabled. The time-base clock may be gated using one of the auto-shutdown/gating signal sources.
  • Input Capture – The value of the 16-bit or 32-bit time base is written to a buffer on certain edge events received from a device input pin. Input Capture signal sources may be gated using one of the auto-shutdown/gating signal sources.
  • Output Compare – A device output pin is set, reset, toggled or pulsed based on register values compared to the 16-bit or 32-bit time base. Register values may be buffered or non-buffered. The output compare signal can be steered to multiple output pins.
The SCCP module include these features:
  • User-Selectable Clock Inputs, Including System Clock and External Clock Input Pins
  • Input Clock Prescaler for Time Base
  • Output Postscaler for Module Interrupt Events or Triggers
  • Synchronization Output Signal for Coordinating Other SCCP Modules with User-Configurable Alternate and Auxiliary Source Options
  • Fully Asynchronous Operation in All Modes and in Low-Power Operation
  • Special Output Trigger for A/D Conversions
  • 16-bit and 32-bit General Purpose Timer Modes with Optional Gated Operation for Simple Time Measurements
  • Capture Modes:
    • 16-bit or 32-bit capture of a time base on an external event
    • Up to a four-level deep FIFO capture buffer
    • Capture source input multiplexer
    • Gated Capture operation to reduce noise-induced false captures
  • Output Compare/PWM Modes:
    • Single Edge and Dual Edge Compare modes
    • External Input mode

The CCP module can be operated only in one of the three major modes (Capture, Compare or Timer) at any time. The other modes are not available unless the module is reconfigured.

A conceptual block diagram for the module is shown in Figure 28-13. All three modes use the Time-Base Generator and the Common Timer register (CCPxTMR). Other shared hardware components, such as comparators and buffer registers, are activated and used as a particular mode requires.

Figure 28-13. CCP Conceptual Block Diagram