37.1 Architectural Overview

Reducing the system clock frequency results in power saving that is roughly proportional to the frequency reduction. The dsPIC33A devices provide an on-the-fly clock switching feature that allows the user application to optimize power consumption by dynamically changing the system clock frequency.

There are two ways to reduce power consumption in dsPIC33A devices:
  1. Instruction-based power-saving modes which include Sleep and Idle.
    • Sleep Mode: In Sleep mode, the CPU, the system clock source and the peripherals that operate on the system clock source are disabled. This is the lowest power mode for the device. Optionally, the peripherals can operate in Sleep mode using specific clock sources. Please refer to the individual peripheral chapter for descriptions on behavior in Sleep mode.

      The SLEEP status flag bit in the Reset Control register (RCON[3]) is set when the device enters Sleep mode.

    • Idle Mode: In Idle mode, the CPU is disabled, but the system clock source continues to operate. The peripherals continue to operate but can optionally be disabled. The IDLE status flag bit in the Reset Control register (RCON[2]) is set when the device enters Idle mode.
    The SLEEP and IDLE status bits are cleared on Power-on Reset (POR) and Brown-out Reset (BOR). These bits can also be cleared in software. For more information on Resets, refer to Resets.
  2. The peripherals can be selectively disabled using the Peripheral Module Disable (PMD) bit of the corresponding peripheral.
Note:
  1. SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device.
  2. Sleep mode does not change the state of the I/O pins.
  3. Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.