36.3.1.2.3 Delay on Wake-up from Sleep

Figure 36-1 shows the wake-up delay from Sleep mode. This delay consists of the voltage regulator delay and the oscillator delay:

Voltage Regulator Delay: This is the time delay for the voltage regulator to transition from the Standby state to the Active state. This delay is required only if Standby mode is enabled for the voltage regulator.
Oscillator Delay: The time delay for the clock to be ready for various clock sources is shown in Table 36-1. For details, refer to Oscillator Module.

Figure 36-1. Wake-up Delay from Sleep Mode

Table 36-1. Oscillator Delay^(1,2,3)
Oscillator Source	Oscillator Start-up Delay	Oscillator Start-up Timer	PLL Lock Time	Total Delay
FRC, FRCDIV16, FRCDIVN	T_OSCD	—	—	T_OSCD
FRCPLL	T_OSCD	—	T_LOCK	T_OSCD + T_LOCK
XT	T_OSCD	T_OST	—	T_OSCD + T_OST
HS	T_OSCD	T_OST	—	T_OSCD + T_OST
EC	—	—	—	—
XTPLL	T_OSCD	T_OST	T_LOCK	T_OSCD + T_OST + T_LOCK
HSPLL	T_OSCD	T_OST	T_LOCK	T_OSCD + T_OST + T_LOCK
ECPLL	—	—	T_LOCK	T_LOCK
LPRC	T_OSCD	—	—	T_OSCD
Note: T_OSCD = Oscillator start-up delay. Crystal oscillator start-up time varies with crystal characteristics, load capacitance, etc. T_OST = Oscillator Start-up Timer delay. T_LOCK = PLL lock time if PLL is enabled.

Note: Refer to Electrical Characteristics for T_VREG, T_OST and T_LOCK specifications and also for the T_OSCD specifications when using the internal FRC or internal LPRC Oscillator.