16.5.7.1 Capture to Trigger

To support the LLC Operating mode, a capture to trigger is available. When triggered, the hardware will capture the time base value, perform a computation and store the result in one of the PGxTRIGy registers. The feature is enabled with the CAPTREN (PGxIOCON1[19]) bit and the CAPTRSEL[1:0] (PGxIOCON1[17:16]) bits define the PGxTRIGy (where y = C, D, E or F) register to store the result. The feature works in conjunction with the time base capture and stores the time base in the PGxCAP register as defined by its control bits.

The trigger value to be stored in the Trigger register is 50% of the high time value, defined as:

PGxTRIGy = (PGxCAP - DTH)/2

Offset and postscaler features can be utilized through the CAPTROFS[4:0] and CAPTRPS[4:0] bitfields, found in the PGxEVT2 register. Capture to Trigger outputs may be postscaled using the CAPTRPS[4:0] control bits to reduce the frequency of PWM events by having PWM events trigger every N cycles. Additionally, the Capture to Trigger outputs can have a one-time offset for a certain number of trigger events using the CAPTROFS[4:0] control bits before the postscaler begins to count the number of trigger events determined by CAPTRPS[4:0].

The CAPTR status bit in PGxSTAT[13] indicates that a new trigger value has been successfully stored in the selected Trigger register. It is cleared when PGxCAP is read or CAPTRSEL[1:0] is written.

Table 16-13 summarizes the operation of the capture features.