8.1.4 FWDT Configuration Register

Legend: R = Readable bit; W = Writable bit

Name: FWDT
Offset: 0x0x7F3030

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       WDTNVMSLWDTRSTEN 
Access R/WR/W 
Reset 11 
Bit 15141312111098 
 WDTENWDTWIN[1:0]RWDTPS[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 10010010 
Bit 76543210 
 RCLKSEL[1:0]SWDTPS[4:0]WINDIS 
Access R/POR/POR/WR/WR/WR/WR/WR/W 
Reset 10010100 

Bit 17 – WDTNVMSL WDT Freeze During Programming Enable bit

ValueDescription
1 Freeze WDT during programming.
0 WDT operation unaffected during programming.

Bit 16 – WDTRSTEN WDT Reset bit

ValueDescription
1 Enables WDT Reset. Run time WDT event will cause a device Reset.
0 Disables WDT Reset. Run time WDT event generates a trap.

Bit 15 – WDTEN Watchdog Timer Enable bit

ValueDescription
1

WDT is enabled in hardware.

0

WDT controlled via the ON bit (WDTCONL[15]).

Bits 14:13 – WDTWIN[1:0] Watchdog Timer Window Select bits

ValueDescription
11 WDT window is 25% (Timer Count > 11xxx...xxxxx for the timer to be cleared)
10 WDT window is 37.5% (Timer Count > 101xx...xxxxx for the timer to be cleared).
01 WDT window is 50% (Timer Count > 1xxxx...xxxxx for the timer to be cleared).
00 WDT Window is 75% (Timer Count >01xxx...xxxxx for the timer to be cleared).

Bits 12:8 – RWDTPS[4:0] Run Mode Watchdog Timer Period Select bits

Configures the postscaler value for Run Mode Counter bits. Refer to Table 34-2.

Bits 7:6 – RCLKSEL[1:0] Watchdog Timer Clock Select bits

ValueDescription
11 LPRC Oscillator
10 BFRC Oscillator
01 Reserved
00

FOSC/4

Bits 5:1 – SWDTPS[4:0] Sleep Mode Watchdog Timer Period Select bits

Configures the postscaler value for Sleep Mode Counter bits. Refer to Table 34-2.
ValueDescription
11111 Divide by 2 ^ 31 = 2,147,483,648
11110 Divide by 2 ^ 30 = 1,073,741,824
...
00001 Divide by 2 ^ 1 = 2
00000 Divide by 2 ^ 1 = 2

Bit 0 – WINDIS Watchdog Window Disable bit

ValueDescription
1 Disables Window mode.
0 Enables Window mode.