29.5.1 SEFC Flash Mode Register
This register can only be written if the WPEN bit is cleared in EEFC_WPMR.
| Name: | EEFC_FMR |
| Offset: | 0x00 |
| Reset: | 0x0C010F00 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ALWAYS1 | CLOE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SCOD | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FWS[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FRDY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 27 – ALWAYS1 Always Written to One
This bit must be always written to 1.
Bit 26 – CLOE Code Loop Optimization Enable
No Flash read should be done during change of this field.
| Value | Description |
|---|---|
| 0 | The opcode loop optimization is disabled. |
| 1 | The opcode loop optimization is enabled if the bit SCOD is reset to 0. |
Bit 16 – SCOD Sequential Code Optimization Disable
No Flash read should be done during change of this field.
| Value | Description |
|---|---|
| 0 | The sequential code optimization is enabled. |
| 1 | The sequential code optimization is disabled. |
Bits 11:8 – FWS[3:0] Flash Wait State
This field defines the number of wait states for read and write operations:
FWS = Number of cycles for Read/Write operations - 1
Note: At hardware reset, this field is set to maximum value 15 to support any clock frequency in the available range.
Bit 0 – FRDY Flash Ready Interrupt Enable
| Value | Description |
|---|---|
| 0 | Flash ready (to accept a new command) does not generate an interrupt. |
| 1 | Flash ready (to accept a new command) generates an interrupt. |