29.5.7 SEFC Write Protection Mode Register
| Name: | EEFC_WPMR |
| Offset: | 0xE4 |
| Reset: | 0x00000010 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERASEWL | USRWP | ERASEWP | LOCKWP | GPNVMWP | WPEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 |
Bits 31:8 – WPKEY[23:0] Write Protection Key
| Value | Name | Description |
|---|---|---|
| 0x454643 | PASSWD |
Writing any other value in this field aborts the write operation. Always reads as 0. |
Bit 7 – ERASEWL Erase and Write Lock
| Value | Description |
|---|---|
| 0 | All Write and Erase commands in the main memory plane as selected by EEFC_FCR.FCMD are enabled. |
| 1 | All Write and Erase commands in the main memory plane as selected by EEFC_FCR.FCMD are disabled until hardware reset. When set to 1, this bit can no longer be modified until hardware reset. |
Bit 4 – USRWP User Signature Write Protection
| Value | Description |
|---|---|
| 0 | Disables the write protection of EEFC_USR and EEFC_KBLR registers. |
| 1 | Enables the write protection of EEFC_USR and EEFC_KBLR registers. |
Bit 3 – ERASEWP Erase and Write Protection
| Value | Description |
|---|---|
| 0 | All Write and Erase commands in the main memory plane as selected by EEFC_FCR.FCMD are enabled. |
| 1 | All Write and Erase commands in the main memory plane as selected by EEFC_FCR.FCMD are disabled. |
Bit 2 – LOCKWP Lock Bit Write Protection
| Value | Description |
|---|---|
| 0 | The ‘Set lock bit’ and ‘Clear lock bit’ commands selected by EEFC_FCR.FCMD are enabled. |
| 1 | The ‘Set lock bit’ and ‘Clear lock bit’ commands selected by EEFC_FCR.FCMD are disabled. |
Bit 1 – GPNVMWP GPNVM Bit Write Protection
| Value | Description |
|---|---|
| 0 | The ‘Set GPNVM bit’ and ‘Clear GPNVM bit’ commands selected by EEFC_FCR.FCMD are enabled. |
| 1 | The ‘Set GPNVM bit’ and ‘Clear GPNVM bit’ commands selected by EEFC_FCR.FCMD are disabled. |
Bit 0 – WPEN Write Protection Enable
See Register Write Protection for the list of registers that can be protected.
| Value | Description |
|---|---|
| 0 | Disables write protection if WPKEY corresponds to 0x454643 (“EFC” in ASCII). |
| 1 | Enables write protection if WPKEY corresponds to 0x454643 (“EFC” in ASCII). |