29.5.3 SEFC Flash Status Register
| Name: | EEFC_FSR |
| Offset: | 0x08 |
| Reset: | 0x00000001 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MECCEMSBL | SECCEMSBL | MECCELSBL | SECCELSBL | MECCEMSBD | SECCEMSBD | MECCELSBD | SECCELSBD | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLSUSP | WPERR | FLERR | FLOCKE | FCMDE | FRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 |
Bit 23 – MECCEMSBL Multiple ECC Error on MSB Part of the Memory Lock Bits
| Value | Description |
|---|---|
| 0 | No multiple error detected on 64 MSB of the Flash memory lock bits since the last read of EEFC_FSR |
| 1 | Multiple errors detected and NOT corrected on 64 MSB of the Flash memory lock bits since the last read of EEFC_FSR |
Bit 22 – SECCEMSBL Single ECC Error on MSB Part of the Memory Lock Bits
| Value | Description |
|---|---|
| 0 | No single error detected on 64 MSB lock bits of the Flash memory since the last read of EEFC_FSR |
| 1 | Single error detected but corrected on 64 MSB of the Flash memory lock bits since the last read of EEFC_FSR |
Bit 21 – MECCELSBL Multiple ECC Error on LSB Part of the Memory Lock Bits
| Value | Description |
|---|---|
| 0 | No multiple error detected on 64 LSB of the Flash memory Lock bits since the last read of EEFC_FSR. |
| 1 | Multiple errors detected and NOT corrected on 64 LSB of the Flash memory Lock bits since the last read of EEFC_FSR. |
Bit 20 – SECCELSBL Single ECC Error on LSB Part of the Memory Lock Bits
| Value | Description |
|---|---|
| 0 | No single error detected on 64 LSB of the Flash memory lock bits since the last read of EEFC_FSR |
| 1 | Single error detected but corrected on 64 LSB of the Flash memory lock bits since the last read of EEFC_FSR |
Bit 19 – MECCEMSBD Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
| Value | Description |
|---|---|
| 0 | No multiple error detected on 64 MSB of the Flash memory data bus since the last read of EEFC_FSR |
| 1 | Multiple errors detected and NOT corrected on 64 MSB of the Flash memory data bus since the last read of EEFC_FSR |
Bit 18 – SECCEMSBD Single ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
| Value | Description |
|---|---|
| 0 | No single error detected on 64 MSB of the Flash memory data bus since the last read of EEFC_FSR |
| 1 | Single error detected but corrected on 64 MSB of the Flash memory data bus since the last read of EEFC_FSR |
Bit 17 – MECCELSBD Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
| Value | Description |
|---|---|
| 0 | No multiple error detected on 64 LSB of the Flash memory data bus since the last read of EEFC_FSR |
| 1 | Multiple errors detected and NOT corrected on 64 LSB of the Flash memory data bus since the last read of EEFC_FSR |
Bit 16 – SECCELSBD Single ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
| Value | Description |
|---|---|
| 0 | No single error detected on 64 LSB of the Flash memory data bus since the last read of EEFC_FSR |
| 1 | Single error detected but corrected on 64 LSB of the Flash memory data bus since the last read of EEFC_FSR |
Bit 5 – FLSUSP Flash Suspended Status (cleared when resuming the programming operation)
| Value | Description |
|---|---|
| 0 | No Flash command is suspended. |
| 1 | The current Flash command is suspended. |
Bit 4 – WPERR Write Protection Error Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No write protection violation occurred since the last read of EEFC_FSR. |
| 1 | A write protection violation occurred since the last read of EEFC_FSR. |
Bit 3 – FLERR Flash Error Status (cleared when a programming operation starts)
| Value | Description |
|---|---|
| 0 | No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed). |
| 1 | A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed). |
Bit 2 – FLOCKE Flash Lock Error Status (cleared on read or by writing EEFC_FCR)
| Value | Description |
|---|---|
| 0 | No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. |
| 1 | Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. |
Bit 1 – FCMDE Flash Command Error Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No invalid commands and no wrong keywords were written in EEFC_FMR. |
| 1 | An invalid command and/or a wrong keyword was/were written in EEFC_FMR. |
Bit 0 – FRDY Flash Ready Status (cleared when Flash is busy)
When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR. It is automatically cleared when the SEFC is busy.
| Value | Description |
|---|---|
| 0 | The SEFC is busy. |
| 1 | The SEFC is ready to start a new command. |