35.7.13 QSPI Instruction Frame Register


Bit	31	30	29	28	27	26	25	24
			PROTTYP[1:0]			DDRCMDEN	DQSEN	APBTFRTYP
Access			R/W	R/W		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
	SMRM			NBDUM[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DDREN	CRM		TFRTYP	ADDRL[1:0]		OPTL[1:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DATAEN	OPTEN	ADDREN	INSTEN	WIDTH[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 29:28 – PROTTYP[1:0] Protocol Type

Values not listed below are considered ‘reserved’.

Value	Name	Description
0	STD_SPI	Standard (Q)SPI Protocol

Bit 26 – DDRCMDEN DDR Mode Command Enable

Value	Name	Description
0	DISABLED	Transfer of instruction field is performed in Single Data Rate mode even if DDREN is written to ‘1’.
1	ENABLED	Transfer of instruction field is performed in Double Data Rate mode if DDREN bit is written to ‘1’. If DDREN is written to ‘0’, the instruction field is sent in Single Data Rate mode.

Bit 25 – DQSEN DQS Sampling Enable

Value	Description
0	Data from the memory are not sampled with DQS signal.
1	Data from the memory are sampled with DQS signal.

Bit 24 – APBTFRTYP Peripheral Bus Transfer Type

Value	Description
0	Peripheral bus register transfer to the memory is a write transfer. Used when TRFTYP is written to ‘0’ and SMRM to ‘1’.
1	Peripheral bus register transfer to the memory is a read transfer. Used when TRFTYP is written to ‘0’ and SMRM to ‘1’.

Bit 23 – SMRM Serial Memory Register Mode

Value	Description
0	Serial Memory registers are written via system bus access. See Instruction Frame Transmission for details.
1	Serial Memory registers are written via peripheral bus access. See Instruction Frame Transmission for details.

Bits 20:16 – NBDUM[4:0] Number Of Dummy Cycles

Defines the number of dummy cycles required by the serial Flash memory before data transfer.

Bit 15 – DDREN DDR Mode Enable

DDRCMDEN defines how the instruction field is sent when Double Data Rate mode is enabled. If DDRCMDEN is at ‘0’, the instruction field is sent in Single Data Rate mode.

Value	Name	Description
0	DISABLED	Transfers are performed in Single Data Rate mode.
1	ENABLED	Transfers are performed in Double Data Rate mode, whereas the instruction field is still transferred in Single Data Rate mode.

Bit 14 – CRM Continuous Read Mode

Value	Name	Description
0	DISABLED	Continuous Read mode is disabled.
1	ENABLED	Continuous Read mode is enabled.

Bit 12 – TFRTYP Data Transfer Type

Value	Name	Description
0	TRSFR_REGISTER	Read/Write of memory register, write of memory page buffer. This configuration implies the following: Either the AHB or the APB interface can be used to initiate the transfer (SMRM bit). Returned data represents the memory register value. If the APB interface is used, the RDRF and TDRE flags help to control the frame. Scrambling is possible only if the APB interface is used. For HyperFlash memories the “target" bit is set to register space in the HyperFlash header.
1	TRSFR_MEMORY	Read/Write accesses to the memory space. This configuration implies the following: Only the System Bus interface can be used to trigger accesses. Access to random location is possible. Address mask is applied and full size accesses only are performed. Internal optimization algorithm is enabled to minimize latency. Data are returned in a system bus protocol compliant way. Seamless scrambling is enabled. Seamless handling of HyperFlash Write Buffer programming command (one command for each data) Seamless protocol-specific page boundary handling Address shift is handled seamlessly (halfword memories, for example).

Bits 11:10 – ADDRL[1:0] Address Length

The ADDRL bit determines the length of the address.

Value	Name	Description
0	8_BIT	8-bit address size
1	16_BIT	16-bit address size
2	24_BIT	24-bit address size
3	32_BIT	32-bit address size

Bits 9:8 – OPTL[1:0] Option Code Length

Determines the length of the option code. The value written in OPTL must be consistent with the value written in the field WIDTH. For example, OPTL = 0 (1-bit option code) is not consistent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4 bits).

Value	Name	Description
0	OPTION_1BIT	The option code is 1 bit long.
1	OPTION_2BIT	The option code is 2 bits long.
2	OPTION_4BIT	The option code is 4 bits long.
3	OPTION_8BIT	The option code is 8 bits long.

Bit 7 – DATAEN Data Enable

Value	Description
0	No data is sent/received to/from the serial Flash memory.
1	Data is sent/received to/from the serial Flash memory.

Bit 6 – OPTEN Option Enable

Value	Description
0	The option is not sent to the serial Flash memory.
1	The option is sent to the serial Flash memory.

Bit 5 – ADDREN Address Enable

Value	Description
0	The transfer address is not sent to the serial Flash memory.
1	The transfer address is sent to the serial Flash memory.

Bit 4 – INSTEN Instruction Enable

Value	Description
0	The instruction is not sent to the serial Flash memory.
1	The instruction is sent to the serial Flash memory.

Bits 3:0 – WIDTH[3:0] Width of Instruction Code, Address, Option Code and Data

Value	Name	Description
0	SINGLE_BIT_SPI	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
1	DUAL_OUTPUT	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
2	QUAD_OUTPUT	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
3	DUAL_IO	Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
4	QUAD_IO	Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
5	DUAL_CMD	Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
6	QUAD_CMD	Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI

Name:	QSPI_IFR
Offset:	0x38
Reset:	0x00000000
Property:	Read/Write