Subsystem 1 Start-Up Sequence

The Core 0 (Application Core) must perform the following steps to bring up the Subsystem 1:

  1. /* Assert reset of core-1 processor & peripherals */ rstc_assert_reset_of_coprocessor(RSTC, RSTC_MR_CPROCEN | RSTC_MR_CPEREN);
  2. /* Disable coprocessor clock */ pmc_disable_cpck();
  3. /* Disable coprocessor Bus Master Clocks (peripheral clocks will be also disabled) */ pmc_disable_cpbmck();
  4. /* Deassert core-1 peripheral reset */ rstc_deassert_reset_of_coprocessor(RSTC, RSTC_MR_CPEREN);
  5. /* Enable coprocessor Bus Master Clocks */ pmc_enable_cpbmck();
  6. _copy_core1_image_into_sram1(); /* Release Coprocessor reset */
  7. -rstc_deassert_reset_of_coprocessor(RSTC, RSTC_MR_CPROCEN);
  8. /* Enable coprocessor clock */ pmc_enable_cpck();

From here Core 1 boots from SRAM1 Memory at address 0x0.

The first step is required for events, mainly reset events, forcing Core 0 to reboot. Depending on the reset source and reset controller configuration, the Metrology subsystem may or may not be reset. On a backup or core reset event (cold reset), the full device is reset and thus the first step is not required.