22.6.16 RTC Tamper Control Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Name: | RTC_TCR |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FGPBRCLR | TAMPCLR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TAMPEN4 | TAMPEN3 | TAMPEN2 | TAMPEN1 | TAMPEN0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 17 – FGPBRCLR Full GPBR Clear
| Value | Name | Description |
|---|---|---|
| 0 | HALF |
If TAMPCLR is set to ‘1’, a tamper event immediately clears GPBR0 to GPBR11. |
| 1 | FULL |
If TAMPCLR is set to ‘1’, a tamper event immediately clears all GPBRs. |
Bit 16 – TAMPCLR Tamper Clear
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE |
A Tamper event does not create an immediate clear on GPBR registers. |
| 1 | ENABLE |
Tamper event on TMP0 or TMP4 generates an immediate clear on GPBR registers. The number of cleared GPBR registers depends on the value of FGPBRCLR. |
Bits 0, 1, 2, 3, 4 – TAMPENx Tampering of TMPx input enabled
| Value | Name | Description |
|---|---|---|
| 0 | TIMESTAMP_OFF | Tamper event on TMPx input is not timestamped. |
| 1 | TIMESTAMP_ON | Tamper event on TMPx input is timestamped. |