22.6.11 RTC Status Clear Command Register

Due to the asynchronous operation of the RTC with respect to the system bus, three slow clock cycles must be completed between two accesses to this register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding status flag in the Status register (RTC_SR).

Name: RTC_SCCR
Offset: 0x1C
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   TDERRCLRCALCLRTIMCLRSECCLRALRCLRACKCLR 
Access WWWWWW 
Reset –––––– 

Bit 5 – TDERRCLR Time and/or Date Free Running Error Clear

If the RTC is configured in UTC mode, this bit has no effect.

Bit 4 – CALCLR Calendar Clear

If the RTC is configured in UTC mode, this bit has no effect.

Bit 3 – TIMCLR Time Clear

If the RTC is configured in UTC mode, this bit has no effect.

Bit 2 – SECCLR Second Clear

Bit 1 – ALRCLR Alarm Clear

Bit 0 – ACKCLR Acknowledge Clear