15.4.7.1 Wake-up Inputs

The wake-up inputs, WKUPx, can be programmed to perform a wake-up of the device from Backup mode. Each input can be enabled by writing a 1 to the corresponding bit, WKUPENx, in the Wakeup Inputs register (SUPC_WUIR). The wake-up level can be selected with the corresponding polarity bit, WKUPTx, also located in SUPC_WUIR.

WKUP0 to WKUP2 pins are located on the VDDBU power rail. All other wake-up inputs are located on the VDD3V3 power rail, and so they cannot be used if VDD3V3 is not supplied.

The resulting signals are wired-ORed to trigger a debounce counter, which is programmed with the WKUPDBC field in the Wakeup Mode register (SUPC_WUMR). SUPC_WUMR.WKUPDBC selects a debouncing period of 3, 32, 512, 4096 or 32768 slow clock cycles. The duration of these periods corresponds, respectively, to about 100 μs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0 selects an immediate wake-up, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of one slow clock period to wake up the core power supply. Once a wake-up event has been detected, the SHDN pin is released.

If an enabled WKUP pin is asserted for a duration longer than the debouncing period, a wake-up of the core voltage regulator is started and the wake-up signals are latched in SUPC_SR. Refer to the figure Wake-up Sources. This allows the user to identify the source of the wake-up. However, if a new wake-up condition occurs, the primary information is lost. No new wake-up can be detected since the primary wake-up condition has disappeared.