2.2 Place and Route

To place and route the design, the Transmit PLL (TX_PLL), XCVR_REF_CLK, PF_XCVR TX and RX lane, and the PF_DDR4_SS_0 must be placed using the I/O Editor.

To place and route the design, perform the following steps:

  1. From the Constraints Manager window, place the Transmit PLL, XCVR_REF_CLK, and PF_XCVR TX and RX lanes using I/O Editor. See the following figure.
    Figure 2-2. I/O Editor—XCVR View
  2. Place the PF_DDR4_SS_0 at NORTH_NW location, see the following figure.
    Figure 2-3. PF_DDR4_SubSystem_0 Placement
  3. From the Design Flow window, double-click Place and Route.

    When place and route is successful, a green tick mark appears, as shown in Figure 2-1.

  4. Right-click Place and Route and select View Report to view the place and route report and log files in the Reports tab.

We recommend viewing the top_place_and_route_constraint_coverage.xml file for place and route constraint coverage.