4.2 Viewing the Enumeration Data

Before you begin, ensure that:

  1. The PolarFire FPGA on one board is programmed with the PCIe Root Port design and the PolarFire FPGA on the other board is programmed with the PCIe Endpoint design.
  2. The two boards are connected through a Microchip PCIe adapter card and powered-up.
  3. LEDs 9, 10, and 11 glow on the Root Port board. This indicates that the PCIe link is up. Otherwise, power-cycle the boards again.

To start the GUI and view the enumeration data, perform the following steps:

  1. From the task bar, click the Start button and select PCIe_Root_Port_GUI.
  2. Click Connect to connect the GUI to the Root Port board, as shown in the following figure.
    Figure 4-1. PCIe Root Port GUI
    The GUI starts detecting the UART COM Port of the Root Port device.
  3. After successfully connecting to the COM port, the Mi-V soft processor enumerates the PCIe EP device and sends the configuration space data to the GUI.
  4. Click Device Info tab to view the Endpoint device information. See the following figure.
    Figure 4-2. Endpoint Device Information
  5. Click Config Space tab to view the basic Type 0 Configuration Settings of the Endpoint.
    Figure 4-3. Endpoint Config Space—Basic
  6. Click Advanced tab to view the MSI Capabilities of the Endpoint, as shown in the following figure.
    Figure 4-4. Endpoint Config Space—Advanced
  7. Similarly, click Power Management Capability and PCIe Capability tabs to view the relevant data.