2.2.1 PLL, DLL, and Lane Controller Placement

PolarFire FPGA I/O pairs are grouped into lanes. Each I/O bank has multiple lanes. Each lane consists of twelve I/Os (six I/O pairs), a lane controller, and a set of high-speed, low-skew clock resources.

All associated I/Os must be placed in one lane. For example, RX_P and RX_N must be placed in the same lane. For more information, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide. The IO Editor shows the placement of the components and I/Os. The PLL of PF_CCC and the PLL, the DLL, and the Lane Controller of PF_IOD_CDR_CCC_C0 are auto placed by Libero SoC.