1.3 Demo Design
(Ask a Question)The following is the data flow for the 1G Ethernet loopback demo design:
- PF_CCC_0 provides the clock to the Mi-V processor and other APB peripherals.
- PF_IOD_CDR_CCC_C0 generates:
- The fabric transmit clock ((TX_CLK_G)) for the CoreTSE block
- The high-speed bank clocks, and drives the high-speed clocks (HS_IO_CLKs) of the PF_IOD_CDR_C0 block for clock recovery
- PF_IOD_CDR_CCC_C0 also generates Delay codes for the PVT compensation.
- Mi-V performs the following functions:
- Executes the application from Tightly Coupled Memory (TCM)
- Configures the ZL30364 clock generation hardware through the CoreSPI IP to generate reference clocks for the VSC PHY and the IOD CDR fabric module
- Configures the Management registers of CoreTSE and VSC PHY
- Sends a request to the CoreTSE IP to negotiate with the on-board VSC8575 PHY
- CoreTSE IP implements 1G Ethernet MAC and is configured in Ten Bit Interface mode (TBI) to interface with the PF_IOD_CDR_C0. The CoreTSE IP has an inbuilt MDIO interface to exchange control and status information with the VSC PHY
- PF_IOD_CDR IP does the following:
- Interfaces with the on-board VSC8575 PHY and forms the SGMII link
- Recovers the data and clock from the incoming RX_P and RX_N ports
- Sends the recovered clock (RX_CLK_R) to the CoreTSE block
- Deserializes the recovered data and sends 10-bit parallel data to CoreTSE
- Receives Ethernet data through the RX_P and the RX_N input pads, gears down the receive data rate, and deserializes the data
- Sends the deserialized data from PF_IOD_CDR_C0:RX_DATA [9:0] to CoreTSE IP: RCG [9:0]
- Loops back the received data at the CoreTSE IP, and sends CoreTSE IP:TCG[9:0] to PF_IOD_CDR_C0:TX_DATA [9:0]
- PF_IOD_CDR_C0 serializes the data, gears up the transmit data rate, and transmits the data to the on-board VSC PHY through the TX_P and TX_N output pads
The following figure shows the hardware implementation of the demo design.
