47.8.8 Synchronization Busy

Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   DATABUF1DATABUF0DATA1DATA0ENABLESWRST 
Access RRRRRR 
Reset 000000 

Bit 5 – DATABUF1 Data Buffer DAC1

This bit is set when DATABUF1 register is written.

This bit is cleared when DATABUF1 synchronization is completed.

ValueDescription
0 No ongoing synchronized access.
1 Synchronized access is ongoing.

Bit 4 – DATABUF0 Data Buffer DAC0

This bit is set when DATABUF0 register is written.

This bit is cleared when DATABUF0 synchronization is completed.

ValueDescription
0 No ongoing synchronized access.
1 Synchronized access is ongoing.

Bit 3 – DATA1 Data DAC1

This bit is set when DATA1 register is written.

This bit is cleared when DATA1 synchronization is completed.

ValueDescription
0 No ongoing synchronized access.
1 Synchronized access is ongoing.

Bit 2 – DATA0 Data DAC0

This bit is set when DATA0 register is written.

This bit is cleared when DATA0 synchronization is completed.

ValueDescription
0 No ongoing synchronized access.
1 Synchronized access is ongoing.

Bit 1 – ENABLE DAC Enable Status

This bit is set when CTRLA.ENABLE bit is written.

This bit is cleared when CTRLA.ENABLE synchronization is completed.

ValueDescription
0 No ongoing synchronization.
1 Synchronization is ongoing.

Bit 0 – SWRST Software Reset

This bit is set when CTRLA.SWRST bit is written.

This bit is cleared when CTRLA.SWRST synchronization is completed.

ValueDescription
0 No ongoing synchronization.
1 Synchronization is ongoing.