47.8.4 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVERRUN1 | OVERRUN0 | RESRDY1 | RESRDY0 | EMPTY1 | EMPTY0 | UNDERRUN1 | UNDERRUN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – OVERRUN1 Overrun Interrupt Enable for Filter Channel 1
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Interrupt Enable for Filter Channel 1 bit, which disables the Filter 1 Overrun interrupt.
| Value | Description |
|---|---|
| 0 | Filter 1 Result Ready interrupt is disabled. |
| 1 | Filter 1 Result Ready interrupt is enabled. |
Bit 6 – OVERRUN0 Overrun Interrupt Enable for Filter Channel 0
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Interrupt Enable for Filter Channel 0 bit, which disables the Filter 0 Overrun interrupt.
| Value | Description |
|---|---|
| 0 | Filter 0 Result Ready interrupt is disabled. |
| 1 | Filter 0 Result Ready interrupt is enabled. |
Bit 5 – RESRDY1 Filter Channel 1 Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Filter Channel 1 Result Ready Interrupt Enable bit, which disables the Filter Channel 1 Result Ready interrupt.
| Value | Description |
|---|---|
| 0 | Filter 1 Result Ready interrupt is disabled. |
| 1 | Filter 1 Result Ready interrupt is enabled. |
Bit 4 – RESRDY0 Filter Channel 0 Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Filter Channel 0 Result Ready Interrupt Enable bit, which disables the Filter Channel 0 Result Ready interrupt.
| Value | Description |
|---|---|
| 0 | Filter 0 Result Ready interrupt is disabled. |
| 1 | Filter 0 Result Ready interrupt is enabled. |
Bit 3 – EMPTY1 Data Buffer 1 Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer 1 Empty Interrupt Enable bit, which disables the Data Buffer 1 Empty interrupt.
| Value | Description |
|---|---|
| 0 | The Data Buffer 1 Empty interrupt is disabled. |
| 1 | The Data Buffer 1 Empty interrupt is enabled. |
Bit 2 – EMPTY0 Data Buffer 0 Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer 0 Empty Interrupt Enable bit, which disables the Data Buffer 0 Empty interrupt.
| Value | Description |
|---|---|
| 0 | The Data Buffer 0 Empty interrupt is disabled. |
| 1 | The Data Buffer 0 Empty interrupt is enabled. |
Bit 1 – UNDERRUN1 Underrun Interrupt Enable for DAC1
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer 1 Underrun Interrupt Enable bit, which disables the Data Buffer 1 Underrun interrupt.
| Value | Description |
|---|---|
| 0 | The Data Buffer 1 Underrun interrupt is disabled. |
| 1 | The Data Buffer 1 Underrun interrupt is enabled. |
Bit 0 – UNDERRUN0 Underrun Interrupt Enable for DAC0
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer 0 Underrun Interrupt Enable bit, which disables the Data Buffer 0 Underrun interrupt.
| Value | Description |
|---|---|
| 0 | The Data Buffer 0 Underrun interrupt is disabled. |
| 1 | The Data Buffer 0 Underrun interrupt is enabled. |