16.14.3 TRISx
Important:
- The TRIS bit associated with the
MCLR pin is read-only and the value is
‘
1’ - Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port
- Unimplemented bits will read back
as ‘
0’
| Name: | TRISx |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRISx7 | TRISx6 | TRISx5 | TRISx4 | TRISx3 | TRISx2 | TRISx1 | TRISx0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISxn Port I/O Tri-state Control
| Value | Description |
|---|---|
1 |
PORTx output driver is disabled. PORTx pin configured as an input (tri-stated) |
0 |
PORTx output driver is enabled. PORTx pin configured as an output |