16.14.6 INLVLx

Input Level Control Register
Important:
  • Refer to the “Pin Allocation Table” for details about pin availability per port
  • Unimplemented bits will read back as ‘0
Name: INLVLx

Bit 76543210 
 INLVLx7INLVLx6INLVLx5INLVLx4INLVLx3INLVLx2INLVLx1INLVLx0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLxn Input Level Select on RX Pin

ValueDescription
1 ST input used for port reads and interrupt-on-change
0 TTL input used for port reads and interrupt-on-change
Refer to the “Pin Allocation Table” for details about pin availability per port Unimplemented bits will read back as ‘0’