7.2 LPDDR3

The following are the guidelines for connecting the device to the LPDDR3 memory:

  • LPDDR3 data nets have dynamic ODT built into the controller and SDRAM. The configurations are 120Ω and 240Ω.
  • DQ lines do not need VTT termination.
  • The characteristic impedance, Zo is typically 50Ω and Zdiff (differential) is 100Ω.

The following table lists the LPDDR3 memory interface features supported in PolarFire SoC devices.

Table 7-4. Interfaces Supported in LPDDR3 Memory Devices
InterfaceLPDDR3
Voltage1.2V
I/O standardHSUL-12
Data rate1333 MT/S-HSIO
TerminationODT for data group
Routing topologyPoint to point

The following figure shows the connectivity between LPDDR3 devices and PolarFire SoC FPGAs.

Figure 7-5. LPDDR3 Interface Example