7.4 LPDDR4

The following are the guidelines for connecting the device to the LPDDR4 memory:

• LPDDR4 nets (Data and CA) have dynamic ODT built into the controller and SDRAM. The ODT configurations available at memory are 40, 48, 60, 80, 120, and 240 and on controller side options are 34, 40, 48, and 60.
• Characteristic impedance for traces: Z₀ (single-ended) typically can be either 50Ω or 40Ω and Z_diff (differential) can be either 100Ω or 80Ω.

LPDDR4 memory comes with different options in terms of channel and rank depending upon the memory size used in the design. Commonly available options are:

• Single-channel, single rank
• Dual-channel, single rank
• Dual-channel, dual ranks

PolarFire SoC LPDDR4 controller supports single rank and single channel. Dual-channel LPDDR4 is supported by concatenating two single-channel on the controller side within FPGA design, and on-board needs to short the Channel-A address of LPDDR4 with the Channel-B address for full memory access.

The following figure shows the PolarFire SoC interface with single-channel, single-rank LPDDR4.

The following figure shows the PolarFire SoC interface with dual-channel, single-rank LPDDR4.

The following table lists the LPDDR4 memory interface features supported in PolarFire SoC FPGA.