3.3 LPDDR3

Automatic initialization of LPDDR3 memory involves the following steps:

  1. Training logic performs HS_IO_CLK-to-SYS_CLK training.
  2. Training logic performs CMD/ADDR to REF_CLK training.
  3. DDR controller waits for the PHY to be ready. At this point, it is assumed that the PHY is outputs stable clocks and signal levels.
  4. CKE is held low for tINIT1. The LPDDR3 specification is 100 ns (minimum), but the controller waits for 100 clock cycles.
  5. CKE is held high for tINIT3. The LPDDR3 specification is 200 μs.
  6. MRW RESET command is issued.
  7. Controller waits for tINIT5.
  8. Controller sequentially issues the initialization calibration command to each active rank. This enables a configuration where all ranks share a ZQ resistor.
  9. Controller waits for tZQINIT after each calibration command is performed.
  10. The MR1, MR2, MR3, MR16, and MR17 registers are configured (in that order) using the MRS command.
  11. Training logic performs write leveling.
  12. Training logic performs DQS gate training.
  13. Training logic aligns read DQ bits.
  14. Training logic aligns read DQS to DQ.
  15. Write calibration is performed.
  16. Normal operation begins.

The controller reinitializes the SDRAM memory when a low-to-high transition is detected on the reinitialization control signal (CTRLR_INIT).

The following figure shows the LPDDR3 automatic initialization flow.

Figure 3-3. Automatic Initialization Flow for LPDDR3 Memory