3.4 LPDDR4 (For PolarFire SoC FPGA Only)

Automatic initialization of LPDDR4 memory (for embedded MSS DDR controller only) involves the following steps:

  1. Training logic performs HS_IO_CLK-to-SYS_CLK training.
  2. DDR controller waits for the PHY to be ready. At this point, it is assumed that the PHY outputs stable clocks and signal levels.
  3. Controller asserts RESET_N, and CKE is held LOW.
  4. Controller deasserts RESET_N after 200 μs, and then deasserts CKE after an additional 2 ms.
  5. Controller waits for tXPR.
  6. The MR13, MR1, MR2, MR3, MR4, MR11, MR16, MR17, MR22, and MR13 registers are configured (in that order) using the MRS command.
  7. Controller waits for 512 clock cycles. During this wait time, the ZQCL (long) command is sent to each rank independently to calibrate the RTT and RON values.
  8. Training logic performs CMD/ADDR to REF_CLK training.
  9. Training logic performs write leveling.
  10. Training logic performs Read Gate (Read DQS gate) training.
  11. Training logic aligns read data (DQ) bits.
  12. Training logic aligns read data strobe (DQS) to DQ.
  13. Write calibration is performed.
  14. Sanity check is performed.
  15. Normal operation begins.

The following figure shows the LPDDR4 automatic initialization flow.

Figure 3-4. Automatic Initialization Flow for LPDDR4 Memory