8.1.1 SmartDebug

SmartDebug Debug DDR Memory GUI capability is automatically provided when a Microchip Fabric DDR Subsystem is hosted in the FPGA fabric and DDR I/O. Microchip’s SmartDebug supports the capability of analyzing and displaying the DDR training data including DDR I/O margin data for all DDR memory controller instances used in a design. The information gathered by the SmartDebug tool provides a quick status of the DDR interface initialization between the FPGA DDR IO and the memory device. The information can be used to make design updates to better match the system interface to the FPGA. For more information, see SmartDebug User Guide .