1.2 Maximum Density Supported by the PolarFire SoC MSS DDR Controller

The MSS DDR Controller requires that the minimum Refresh Cycle Interval (tREFI) must be greater than 4 times the Refresh Cycle time (tRFC). The Refresh Cycle Interval is the period between successive refresh commands, and the Refresh Cycle time is the duration of a refresh operation. DDR manufacturers specify the tREFI for the DDR memory’s operating case temperature. The preceding requirements restrict the maximum supported DDR die density at higher temperatures for DDR4 and LPDDR4. This restriction does not apply to DDR3 and LPDDR3 memories.

The Refresh Cycle time is proportional to the memory die density. The following table lists the maximum supported DDR die density at different case temperatures.

Table 1-1. PolarFire SoC FPGA Maximum Die Density
Device Maximum Die Density
Memory Case Temperature−40 < Tc1 < 85 ℃ −40 < Tc < 95 ℃−40 < Tc < 105 ℃−40 < Tc < 125 ℃
DDR4 16 Gb 16 Gb8 Gb2 Gb
LPDDR4 16 Gb4 Gb4 Gb4 Gb
Note:
  1. Tc is the case temperature of the DDR Memory.

DDR memory vendors integrate one or more dies in a single component to create memory modules of higher density, and one can use several components to create a data width of x32. The MSS DDR controller is designed to support dual ranks for DDR4.

The maximum supported memory density is based on the following criteria:
  • The DDR memory component die size must be within the maximum die density mentioned in Table 1-1 for a given DDR operating case temperature
  • More than one component or die can be used to enhance data width to up to x32 for DDR4
  • Dual Channel can be used to enhance data width to up to x32 for LPDDR4
  • Dual Rank is supported for DDR4

The following table lists the maximum supported memory density at different case temperatures, for the PolarFire SoC MSS DDR controller.

Table 1-2. PolarFire SoC FPGA Maximum Supported Memory Density
Device Maximum Memory Density
Memory Case Temp −40 < Tc1 < 85 ℃ −40 < Tc < 95 ℃−40 < Tc < 105 ℃−40 < Tc < 125 ℃
DDR4 128 Gb 128 Gb 32 Gb 8 Gb
LPDDR4 32 Gb 8 Gb8 Gb 8 Gb
Note:
  1. Tc is the case temperature of the DDR Memory.
Important: FPGA temperature grades are denoted by “Tj”, the FPGA junction temperature. Therefore, FPGA “Tj” is different from the DDR memory “Tc”. Typically, “Tj” is higher than “Tc”.

Memory Selection Guidelines

The following examples provide the memory selection guidelines for DDR4 and LPDDR4.

  • Example 1: DDR4

    Requirement: 4 GB (32 Gb) DDR4 memory at an operating case temperature (Tc) of up to 105 ℃

    Guideline: A memory device that uses a 16 Gb die in 2Gx8 configuration must not be selected as the maximum supported die size at Tc = 105 ℃ is 8 Gb. Instead, you can choose one of the following options:

    • Option A: Stack 2 components of DDR memory that uses 8 Gb die in 1Gx8 configuration and dual ranks
    • Option B: Stack 4 components of DDR memory that uses 8 Gb die in 1Gx8 configuration and single rank
  • Example 2: LPDDR4

    Requirement: 1 GB (8 Gb) LPDDR4 memory at an operating case temperature (Tc) of up to 95 ℃

    Guideline: A memory device that uses 8 Gb die in a 512Mx16 configuration must not be selected as the maximum supported die size at Tc = 95 ℃ is 4 Gb. Instead, choose a device that uses 4 Gb die in 256Mx32 (two channels of 16-bit data width) to build the 8 Gb LPDDR4 memory.

Some examples of possible memory configurations are provided in the following table.

Table 1-3. Memory Configuration Examples
Memory Type Configuration1Number of Components2Component Density3Total Data WidthRank/ChannelTotal Density
DDR4 (Twin Die)x84 16 Gbx32 Dual Rank 128 Gb
DDR4 x84 16 Gbx32 Single Rank64 Gb
DDR4x848 Gbx32Single Rank32 Gb
LPDDR4 (Twin Die)x16 116 Gbx32Dual Channel 32 Gb
LPDDR4 (Twin Die)x1614 Gbx32Dual Channel8 Gb
Note:
  1. For DDR4, “Configuration” indicates the data bus width of the Chip. For LPDDR4, “Configuration” indicates the width of the channel.
  2. “Number of Components” indicates the quantity of memory chips needed.
  3. “Component Density” indicates the die size in the memory.