8 List of Registers

I2C_BASE (0x20)

Bit [7]: Not used

Bits [6:0]: Base address for register level I2C access

OPERATION (0x22)

For a description of this register contents, see the OPERATION command in the PMBus Commands section.

ON_OFF_CONFIG (0x23)

For a description of this register content, see the ON_OFF_CONFIG command in the PMBus Commands section.

WRITE_PROTECT (0x24)

For a description of this register contents, see the WRITE_PROTECT command in the PMBus Commands section. Note that the protections in this register only apply to PMBus access. All access is always available via the direct register level I2C access.

MASK_BYTE_VOUT (0x25)

This register contains the mask byte applied to the STATUS_VOUT register using the SMBALERT_MASK command.

MASK_BYTE_IOUT (0x26)

This register contains the mask byte applied to the STATUS_IOUT register using the SMBALERT_MASK command.

MASK_BYTE_INPUT (0x27)

This register contains the mask byte applied to the STATUS_INPUT register using the SMBALERT_MASK command.

MASK_BYTE_TEMP (0x28)

This register contains the mask byte applied to the STATUS_TEMP register using the SMBALERT_MASK command.

MASK_BYTE_CML (0x29)

This register contains the mask byte applied to the STATUS_CML register using the SMBALERT_MASK command.

VOUT_MODE (0x2B)

For a description of this register contents, see the VOUT_MODE command in the PMBus Commands section.

VOUT_COMMAND_LOWER (0x2C)

For a description of this register contents, see the VOUT_COMMAND command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x2D.

VOUT_COMMAND_UPPER (0x2D)

For a description of this register contents, see the VOUT_COMMAND command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x2C.

VOUT_MAX_LOWER (0x2E)

For a description of this register contents, see the VOUT_MAX command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x2F.

VOUT_MAX_UPPER (0x2F)

For a description of this register contents, see the VOUT_MAX command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x2E.

VOUT_MARGIN_HIGH_LOWER (0x30)

For a description of this register contents, see the VOUT_MARGIN_HIGH command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x31.

VOUT_MARGIN_HIGH_UPPER (0x31)

For a description of this register contents, see the VOUT_MARGIN_HIGH command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x30.

VOUT_MARGIN_LOW_LOWER (0x32)

For a description of this register contents, see the VOUT_MARGIN_LOW command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x33.

VOUT_MARGIN_LOW_UPPER (0x33)

For a description of this register contents, see the VOUT_MARGIN_LOW command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x32.

VOUT_TRANSITION_RATE_LOWER (0x34)

For a description of this register contents, see the VOUT_TRANSITION_RATE command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x35.

VOUT_TRANSITION_RATE _UPPER (0x35)

For a description of this register contents, see the VOUT_ TRANSITION_RATE command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x34.

VIN_ON_LOWER (0x38)

For a description of this register contents, see the VIN_ON command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x39.

VIN_ON _UPPER (0x39)

For a description of this register contents, see the VIN_ON command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x38.

VIN_OFF_LOWER (0x3A)

For a description of this register contents, see the VIN_OFF command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x3B.

VIN_OFF _UPPER (0x3B)

For a description of this register contents, see the VIN_OFF command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x3A.

VOUT_OV_FAULT_LIMIT_LOWER (0x3E)

For a description of this register contents, see the VOUT_OV_FAULT_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x3F.

VOUT _OV_FAULT_LIMIT_UPPER (0x3F)

For a description of this register contents, see the VOUT_OV_FAULT_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x3E.

VOUT _OV_FAULT_RESPONSE (0x40)

For a description of this register contents, see the VOUT_OV_FAULT_RESPONSE command in the PMBus Commands section.

VOUT _OV_WARN_LIMIT_LOWER (0x41)

For a description of this register contents, see the VOUT_OV_WARN_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x42.

VOUT _OV_WARN_LIMIT_UPPER (0x42)

For a description of this register contents, see the VOUT_ OV_WARN_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x41.

VOUT _UV_WARN_LIMIT_LOWER (0x43)

For a description of this register contents, see the VOUT_UV_WARN_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x44.

VOUT _UV_WARN_LIMIT_UPPER (0x44)

For a description of this register contents, see the VOUT_ UV_WARN_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x43.

VOUT _UV_FAULT_LIMIT_LOWER (0x45)

For a description of this register contents, see the VOUT_UV_FAULT_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x46.

VOUT _UV_FAULT_LIMIT_UPPER (0x46)

For a description of this register contents, see the VOUT_ UV_FAULT_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x45.

VOUT _UV_FAULT_RESPONSE (0x47)

For a description of this register contents, see the VOUT_UV_FAULT_RESPONSE command in the PMBus Commands section.

IOUT_OC_FAULT_LIMIT_LOWER (0x48)

For a description of this register contents, see the IOUT_OC_FAULT_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x49.

IOUT_OC_FAULT_LIMIT_UPPER (0x49)

For a description of this register contents, see the IOUT_OC_FAULT_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x48.

IOUT_OC_FAULT_RESPONSE (0x4A)

For a description of this register contents, see the IOUT_OC_FAULT_RESPONSE command in the PMBus Commands section.

VIN_OV_FAULT_LIMIT_LOWER (0x52)

For a description of this register contents, see the VIN_OV_FAULT_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x53.

VIN_OV_FAULT_LIMIT_UPPER (0x53)

For a description of this register contents, see the VIN_OV_FAULT_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x52.

VIN_OV_FAULT_RESPONSE (0x54)

For a description of this register contents, see the VIN_OV_FAULT_RESPONSE command in the PMBus Commands section.

VIN_UV_WARN_LIMIT_LOWER (0x55)

For a description of this register contents, see the VIN_UV_WARN_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x56.

VIN_UV_WARN_LIMIT_UPPER (0x56)

For a description of this register contents, see the VIN_UV_WARN_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x55.

POWER_GOOD_ON_LOWER (0x57)

For a description of this register contents, see the POWER_GOOD_ON command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x58.

POWER_GOOD_ON_UPPER (0x58)

For a description of this register contents, see the POWER_GOOD_ON command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x57.

TON_DELAY_LOWER (0x5B)

For a description of this register contents, see the TON_DELAY command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x5C.

TON_DELAY_UPPER (0x5C)

For a description of this register contents, see the TON_DELAY command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x5B.

TON_RISE_LOWER (0x5D)

For a description of this register contents, see the TON_RISE command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x5E.

TON_RISE_UPPER (0x5E)

For a description of this register contents, see the TON_RISE command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x5D.

TON_MAX_FAULT_LIMIT_LOWER (0x5F)

For a description of this register contents, see the TON_MAX_FAULT_LIMIT command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x60.

TON_MAX_FAULT_LIMIT_UPPER (0x60)

For a description of this register contents, see the TON_MAX_FAULT_LIMIT command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x5F.

TON_MAX_FAULT_RESPONSE (0x61)

For a description of this register contents, see the TON_MAX_FAULT_RESPONSE command in the PMBus Commands section.

TOFF_DELAY_LOWER (0x62)

For a description of this register contents, see the TOFF_DELAY command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x63.

TOFF_DELAY_UPPER (0x63)

For a description of this register contents, see the TOFF_DELAY command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x62.

TOFF_FALL_LOWER (0x64)

For a description of this register contents, see the TOFF_FALL command in the PMBus Commands section. This register contains the low byte of the data for that command. This register requires an atomic write with register 0x65.

TOFF_FALL_UPPER (0x65)

For a description of this register contents, see the TOFF_FALL command in the PMBus Commands section. This register contains the high byte of the data for that command. This register requires an atomic write with register 0x64.

MFR_ID_COUNT (0x66)

This register does not have a direct PMBus counterpart but is used in the PMBus MFR_ID command. This command is a SMBus block read or a SMBus block write command. This register holds the byte count for these SMBus transactions. Note that there are only 3 data bytes available for the MFR_ID command.

MFR_ID_1 (0x67)

This register contains the first byte used in the PMBus MFR_ID command.

MFR_ID_2 (0x68)

This register contains the second byte (if used) in the PMBus MFR_ID command.

MFR_ID_3 (0x69)

This register contains the third byte (if used) in the PMBus MFR_ID command.

MFR_MODEL_COUNT (0x6A)

This register does not have a direct PMBus counterpart but is used in the PMBus MFR_ID command. This command is a SMBus block read or a SMBus block write command. This register holds the byte count for these SMBus transactions. Note that there is only 1 data byte available for the MFR_MODEL command.

MFR_MODEL (0x6B)

This register contains the byte used in the PMBus MFR_MODEL command.

MFR_REVISION_COUNT (0x6C)

This register does not have a direct PMBus counterpart but is used in the PMBus MFR_REVISION command. This command is a SMBus block read or a SMBus block write command. This register holds the byte count for these SMBus transactions. Note that there is only 1 data byte available for the MFR_MODEL command.

MFR_REVISION (0x6D)

This register contains the byte used in the PMBus MFR_REVISION command.

CAPABILITY (0x6E)

For a description of this register contents, see the CAPABILITY command in the PMBus Commands section. This register contains the low byte of the data for that command.

BUS_VOLTAGE (0x7A)

This register sets the bus voltage for the I²C bus.

Bit [4]:

0: Enable PLL, Mode B

1: Disable PLL, Mode A (default)

Bit [3]:

0: Power Good based on POWER_GOOD_ON command value

1: Power Good based on DAC (Default)

Bit [2]:

0: 1.8V to 2.5V

1: 3.3V to 5V

All other bits are reserved.

OTP_ON (0x89)

This register sets the bus voltage for the I²C bus.

Bit [1]:

0: Do not initiate write of user memory

1: Initiate write of user memory

Bit [0] is reserved.

All other bits are unused.

CLEAR_STATUS (0x8C)

This register sets the bus voltage for the I²C bus.

Bit [0]:

0: Do not clear status flags

1: Clear status flags

Bits [7] and [2] are reserved.

All other bits are unused.

USER_OTP_POINTER (0x92)

This register shows the number of remaining write allowed to the user NVM area.

Bits [7:4]:

0001: 9 writes remaining

0010: 8 writes remaining (default after factory trimming and initial setup)

0011: 7 writes remaining

0100: 6 writes remaining

0101: 5 writes remaining

0110: 4 writes remaining

0111: 3 writes remaining

1000: 2 writes remaining

1001: 1 write remaining

1010: 0 writes remaining

Bits [3:0] are unused.

STATUS (0x93)

This register shows the status flags for the part.

Bit [7]: Power Good status

Bit [6]: Overvoltage status

Bit [5]: Overcurrent status

Bit [4]: Temperature status

Bit [3]: Enable pin status

Bit [2]: Not used

Bit [1]: User NVM write status

Bit [0]: Status cleared indicator. This is a mirror of register 0x8C, bit 0.

IC_REV_BYTE_COUNT (0x94)

This register does not have a direct PMBus counterpart but is used in the PMBus IC_DEVICE_REV command. This command is a SMBus block read or a SMBus block write command. This register holds the byte count for these SMBus transactions. Note that there is only 1 data byte available for the IC_DEVICE_REV command.

IC_REV (0x95)

This register contains the byte used in the PMBus IC_DEVICE_REV command.

IC_DEV_ID_COUNT (0x96)

This register does not have a direct PMBus counterpart but is used in the PMBus IC_DEVICE_ID command. This command is a SMBus block read or a SMBus block write command. This register holds the byte count for these SMBus transactions. Note that there is only 1 data byte available for the IC_DEVICE_REV command.

IC_DEV_ID (0x97)

This register contains the byte used in the PMBus IC_DEVICE_ID command.

PVIN_REPORT_LOWER (0x9A)

For a description of this register contents, see the READ_VIN command in the PMBus Commands section. This register contains the low byte of the data for that command.

PVIN_REPORT_UPPER (0x9B)

For a description of this register contents, see the READ_VIN command in the PMBus Commands section. This register contains the high byte of the data for that command.

VOUT_REPORT_LOWER (0xA0)

For a description of this register contents, see the READ_VOUT command in the PMBus Commands section. This register contains the low byte of the data for that command.

VOUT_REPORT_UPPER (0xA1)

For a description of this register contents, see the READ_VOUT command in the PMBus Commands section. This register contains the high byte of the data for that command.

TEMP_REPORT_LOWER (0xA2)

For a description of this register contents, see the READ_TEMPERATURE command in the PMBus Commands section. This register contains the low byte of the data for that command.

TEMP_REPORT_UPPER (0xA3)

For a description of this register contents, see the READ_TEMPERATURE command in the PMBus Commands section. This register contains the high byte of the data for that command.

VCC_REPORT_UPPER (0xA5)

This register contains the high byte of a linear 11 format representation of the VCC voltage of the part. The exponent for this calculation, with a value of -5, is in bits [7:3].

ADDR_REPORT_LOWER (0xA6)

This register contains the low byte of the result of the ADC converter that looks at the ADDR pin for determining the address offset to apply to the base addresses for both PMBus and direct register access.

ADDR_REPORT_UPPER (0xA7)

This register contains the high byte of the result of the ADC converter that looks at the ADDR pin for determining the address offset to apply to the base addresses for both PMBus and direct register access.