2 Functional Description

The MCPF1412M06 is a user-friendly, fully integrated, and highly efficient DC/DC regulator. Its operation, including output voltage and system optimization parameters, can be programmed via the I²C/PMBus™ protocol. It employs a proprietary modulator to ensure rapid transient response. The modulator features internal compensation, making it suitable for a wide range of applications with various types of output capacitors, without encountering loop stability issues.

The MCPF1412M06 is a versatile device that offers significant flexibility for configuration and system monitoring through the I²C/PMBus™ interface. Additionally, it supports standalone operation without a digital interface, allowing designers to easily configure output voltages using simple resistor divider adjustments and monitor the system via the Power Good output.

The MCPF1412M06 employs an interleaved buck converter design, which minimizes voltage stress on internal power components, leading to a more compact size but with switching losses similar to those of a conventional interleaved buck converter with the same rating. Additionally, it features an inherent current-sharing mechanism between the two phases.

The MCPF1412M06 features an integrated Low Drop-Out (LDO) regulator that supplies the DC bias voltage for its internal circuitry, typically outputting 5.2V. For single-rail operation with internal bias, connect the VIN pin to the PVIN pin (see Figure 2-1). When using an external bias voltage, connect the VIN pin to the VCC pin to bypass the internal LDO regulator (see Figure 2-2). A separate pin (PVCC) is provided for driver bias and should be connected to VCC in the application circuit. The supply voltage, whether internal or external, increases with VIN and does not require enabling via the EN pin. Therefore, I²C/PMBus™ communication can commence once the following conditions are met:

• The VCC_UVLO start threshold is surpassed
• Memory contents are loaded
• Initialization is complete
• The address offset is read

The I²C bus can be pulled up to either VCC or a system I²C bus voltage. The MCPF1412M06 allows for two I²C bus voltage ranges, selectable via the user register bit Bus_voltage_sel, as shown below:

The MCPF1412M06 features user-configurable registers to set its I²C and PMBus™ base addresses. By default, the I²C base address is 0x08, and the PMBus™ base address is 0x70. An offset ranging from 0 to 15 is determined by connecting the ADDR pin to the AGND pin, either directly or via a resistor. At startup, an address detector measures the resistance of this connection to set the offset, which is then added to the base I²C address to establish the address for I²C communication with the MCPF1412M06. The same offset is added to the base PMBus™ address to set the PMBus™ communication address.

To select offsets from 0 to 15, connect the pins as follows:

• 0 – 0Ω (short ADDR to AGND)
• +1 – 1.13 kΩ
• +2 – 1.87 kΩ
• +3 – 2.61 kΩ
• +4 – 3.4 kΩ
• +5 – 4.12 kΩ
• +6 – 4.87 kΩ
• +7 – 5.62 kΩ
• +8 – 6.34 kΩ
• +9 – 7.15 kΩ
• +10 – 7.87 kΩ
• +11 – 8.66 kΩ
• +12 – 9.31 kΩ
• +13 – 10.2 kΩ
• +14 – 11 kΩ
• +15 – 12.1 kΩ

The MCPF1412M06 features an internal digital soft start circuit designed to manage the output voltage rise-time and limit current surges during start-up. When VCC surpasses its start threshold (VCC_UVLO_(START)), the MCPF1412M06 exits reset mode, initiating the loading of non-volatile memory contents into working registers and calculating the address offset as previously described. After initialization, the internal soft start ramps up towards the set reference voltage at a rate specified by the TON_RISE registers (associated with the TON_RISE command), provided the following conditions are met:

1. A valid enable signal is detected, as defined by the Enable pin, Operation register, ON_OFF_CONFIG register, input voltage PVIN, and PVIN UVLO threshold corresponding to the VIN_ON registers.
2. The internal pre-charge circuit ensures balanced PVIN/2 voltages across all FETs when the device begins switching.

During initial start-up, the MCPF1412M06 operates with minimal high-drive (HDrv) pulses until the output voltage increases (refer to Switching frequency and minimum values for ON-time, OFF-time). The ON time is increased until VOUT reaches the target value set by the VOUT_COMMAND registers. For optimal start-up performance, it is recommended to use a 100Ω resistor connected in parallel with the output capacitors (C_OUT). A minimum wait time of 600Ω × C_OUT is advised between successive power or Enable cycling operations. For instance, with a 100Ω resistor across four 47 μF output capacitors, a new Enable assertion should not occur until at least 78 ms (allowing the reduction of capacitance at a bias of 1V - see Design Example) after disabling the MCPF1412M06.

Overcurrent Protection (OCP) and Overvoltage Protection (OVP) are active during soft start to safeguard the MCPF1412M06 from short circuits and excessive voltages.

A resistor divider can be utilized with a standard MCPF1412M06 device to set the desired output voltage (Figure 2-4). This provides system designers with the flexibility to configure all power rails in the system across the entire output voltage range (0.6–1.8V) using a single component.

The following equation describes the appropriate resistor divider selection to set the output voltage using an MCPF1412M06 programmed to 0.6V:

Where:

R_TOP and R_BOTTOM are in kΩ.

It is recommended that system designers place a capacitor (C_FF in Figure 5-1) of 47 pF to 470 pF in parallel with R_TOP. 4.12 kΩ is suggested as a value for R_TOP. The recommended value for R_BOTTOM depends on the output voltage, as shown in the table below. Designers should validate these values in their specific applications.

Alternatively, the output voltage can be set using I²C/PMBus™ commands (see PMBus Commands) or the corresponding user registers, instead of an external resistor divider. The table below lists VOUT_COMMAND codes to set the specified voltages. The MCPF1412M06 supports this command with a resolution of 1/256V.

The MCPF1412M06 features two shutdown mechanisms:

1. Hard Shutdown or Load-Dependent Decay:

   A valid hard-disable is detected based on the Enable pin, Operation register, ON_OFF_CONFIG register, input voltage PVIN, and PVIN UVLO threshold corresponding to the VIN_ON registers. Both drivers are immediately turned OFF, and the soft start is pulled down instantly.

2. Soft-Stop or Controlled Ramp Down:

   A valid soft-OFF request is detected based on the Enable pin, Operation register, and ON_OFF_CONFIG register. After a delay defined by the TOFF_DELAY registers, the SS signal gradually decreases to 0 over a period specified by the TOFF_FALL registers. The drivers are disabled only when the SS signal reaches 0, causing the output voltage to follow the SS signal down to 0.

By default, the device is set for hard shutdown. Shutdown using PVIN is always a hard shutdown.

The switching frequency of the MCPF1412M06 is influenced by the output voltage and can operate in one of two modes:

• Mode A: Pseudo constant-frequency COT mode (default)
• Mode B: PLL-modulated COT mode

For the default output voltage of 0.6V, the switching frequency is typically 470 kHz, and the device functions in Mode A. In this mode, if the output voltage is adjusted using an external resistor divider, the switching frequency automatically adapts to the correct value:

When the output voltage is configured via the VOUT_COMMAND user registers instead of an external resistor divider, Mode B should be selected. To implement this, the user must enable the Phase-Locked Loop (PLL), which is disabled by default, and toggle the Enable pin. This action automatically sets the switching frequency to the factory-programmed values listed in the table below. The PLL adjusts the ON-time to ensure a constant switching frequency regardless of the load.

With either approach, system designers do not need to worry about selecting the switching frequency. When the input voltage is significantly higher than the target output voltage, the high side MOSFETs are switched ON for shorter durations. The shortest reliable ON-time is defined by the minimum ON-time (T_ON(MIN)). During start-up, when the output voltage is very low, the MCPF1412M06 operates with the minimum ON-time.

The maximum conversion ratio is influenced by two factors:

1. When the input voltage is low, relative to the target output voltage, the Control MOSFET is switched ON for longer durations. The shortest OFF-time is defined by the minimum OFF-time (T_OFF(MIN)). During this period, the Synchronous MOSFET remains ON, and its current is monitored for overcurrent protection. This determines the minimum input voltage that can still allow the device to regulate its output at the target voltage.
2. To maintain balanced switching amplitudes in both phases, this topology requires no overlap between the high sides of the two phases, unlike a conventional buck topology. This imposes theoretical maximums of 50% on the duty cycle of each phase and 25% on the conversion ratio. In practice, considering circuit delays and dead-times, the conversion ratio should not exceed 16% at full load.

The maximum conversion ratio is influenced by both system efficiency and load transient requirements. It is recommended that system designers validate these values in their specific applications.

The switching of the part can be synchronized to an external clock. The external clock frequency must be more than twice the switching frequency calculated in the previous section. To use the SYNC function, the part must be operating in mode B: PLL-modulated constant-requency COT mode. To activate this mode, write 0 to bit[4] of the BUS_VOLTAGE (0x7A) register. The per phase switching frequency of the converter will be one half of the applied external clock, as the aggregate switching frequency is synchronized to the external clock. The maximum frequency is 2 MHz per phase or 4 MHz aggregate.

The Enable (EN) pin serves multiple purposes:

• By default, according to the ON_OFF_CONFIG command, it controls the power state of the MCPF1412M06. It features a precise threshold monitored by the UVLO circuit. If left unconnected, an internal 1 MΩ resistor pulls it down to prevent accidental activation of the MCPF1412M06.
• It can be utilized to establish a precise input voltage UVLO. The EN pin's input is derived from the PVIN voltage through a set of resistive dividers (Figure 2-1). Users can adjust the UVLO threshold voltage by selecting different resistor ratios, allowing for finer control over the PVIN UVLO voltage levels than the VIN_ON/VIN_OFF commands provide.
• It can also be used to monitor other power rails for specific power sequencing schemes (Figure 2-5).

Overcurrent Protection (OCP) is achieved by monitoring the voltage across the channel RDS(ON) of the Synchronous MOSFET. When this surpasses the OCP threshold, a fault condition is triggered.

This approach offers several advantages:

• Ensures precise overcurrent protection without compromising converter efficiency (the current sensing is lossless)
• Lowers costs by eliminating the need for a current-sense resistor
• Minimizes layout-related noise issues

The OCP threshold is set by the IOUT_OC_FAULT_LIMIT command (or corresponding user registers) and can be programmed in 0.5A increments, up to a maximum of 16A. The recommended minimum overcurrent threshold is 10A. The OCP threshold is internally compensated to remain nearly constant across different ambient temperatures.

When the current exceeds the OCP threshold, the PG and SS signals are pulled low. The Synchronous MOSFET stays ON until the current drops to 0, after which the MCPF1412M06 enters hiccup. Both the Control MOSFET and the Synchronous MOSFET remain OFF during the hiccup-blanking period. After this period, the MCPF1412M06 attempts to restart. If an overcurrent fault is still present, the previous actions are repeated. The MCPF1412M06 stays in hiccup mode until the overcurrent fault is resolved. The MCPF1412M06 can also be reprogrammed to enter a latched shutdown mode upon detecting an overcurrent fault.

Overvoltage Protection (OVP) is achieved by monitoring the voltage at the FB pin. If the FB pin voltage surpasses the output OVP threshold for more than the output OVP delay (typically 5 μs), a fault condition is triggered.

The OVP threshold is determined by the VOUT_OV_FAULT_LIMIT command (or the corresponding user registers). This command enables the overvoltage level to be set relative to the output voltage, with a resolution of 1/256V. Internally, these values are rounded to one of four settings, as indicated in the table below.

The default setting is 120%. All MOSFETs are immediately switched OFF, and the PG pin is pulled low. The MOSFETs stay latched off until reset by cycling either VCC or EN. Figure 2-7 illustrates a timing diagram for overvoltage protection.

The MCPF1412M06 issues warnings for output overvoltage and undervoltage, and provides protection against output undervoltage faults. These functions are controlled by three commands (or their corresponding user registers):

• VOUT_OV_WARN_LIMIT
• VOUT_UV_WARN_LIMIT
• VOUT_UV_FAULT_LIMIT

The threshold mechanism for these warnings differs from the overvoltage protection mechanism: the warnings use a digital comparison of the digitized and processed VOUT telemetry against the thresholds, while the overvoltage protection uses an all-analog signal path and an internal high-speed comparator.

The MCPF1412M06 includes an internal temperature sensing feature. The Overtemperature Protection (OTP) threshold is determined by a fixed internal threshold, set at 145°C. This threshold is monitored by an internal analog comparison. If the temperature exceeds this limit, the device halts switching and turns OFF all MOSFETs until the temperature falls below the threshold, at which point it automatically restarts.

Power Good (PG) behavior is defined through the PGControl register bits and the POWER_GOOD_ON command. When the PGControl bit is enabled, the PMBus™ command can set the upper Power Good threshold relative to the output voltage with a resolution of 1/256V. Internally, these values are rounded to one of four settings, as illustrated in the table below.

The default setting is 90%, meaning the PG signal will be activated when the voltage at the FB pin surpasses 90% of the VOUT_COMMAND setting (default 0.6V). A 5% hysteresis is applied, creating a lower threshold. If the voltage at the FB pin falls below this lower threshold, the PG signal will be deactivated.

Figure 2-8 illustrates the case where the PGControl bit is set to 1.

The behavior remains consistent during start-up and normal operation. The PG signal is asserted when:

• Both EN and VCC exceed their thresholds
• No faults are present (including overcurrent, overvoltage, and overtemperature)
• VOUT is within the target range (monitored continuously to ensure FB is above the PG threshold)

With the PGControl bit set to '0' the operation is as shown in Figure 2-9.

During normal operation, the PG signal functions identically to when the PGControl bit is set to '1'. However, at start-up, the PG signal is asserted once FB is within 2% of the target output voltage, rather than when FB surpasses the upper PG threshold. The MCPF1412M06 also includes an additional PMOS in parallel with the NMOS, internally connected to the PG pin (see Block Diagram). This PMOS ensures that the PG signal remains at a logic low level, even if VCC is low and the PG pin is pulled up to an external voltage other than VCC.