1 Pin Configuration

Pin Number Name Description
1SW2Test Pin
2VINInput voltage and input to the LDO regulator.
3ENEnable pin. Turns the MCPF1412M06 ON and OFF. A resistor divider can be used on this pin to create an external UVLO condition.
4PVCCInput supply for the driver circuits. Connect to VCC.
5VCCSupply voltage. This is used as either a bypass capacitor connection for the internal LDO or as a connection point for an external bias voltage.
6FBFeedback voltage to the device. Connect the tap of a voltage divider across the output voltage to this pin to set the output voltage value.
7, 22AGNDSignal level ground for the converter and the internal control circuitry. Connect this to the ground plane of the application.
8VOUTOutput voltage of the regulator. Connect output filter capacitors and a 100Ω resistor from this pin to PGND.
9PGPower Good status indicator. An open drain FET pulls this pin down when Power Good is not asserted. Connect 49.9 kΩ from this pin to VCC or an external 5V rail.
10ADDRAddress pin. Connect a resistor from this pin to AGND to set the I2C address of the part.
11SYNCSynchronization input to synchronize the switching to an external source. Connect to AGND if not used.
12SDAI2C/PMBus data I/O pin. Pull this pin up to the bus voltage with 4.99 kΩ or connect to AGND if not used.
13SCLI2C/PMBus clock pin. Pull this pin up to the bus voltage with 4.99 kΩ or connect to AGND if not used.
14SALERTSMBAlert# line. Pull this up to bus voltage with a 4.99 kΩ resistor.
15SW1Optional connection for a capacitor to CB. A 0.1 to 1 μF, 16V or higher rated MLCC capacitor is recommended.
16, 20, 21PGNDPower Ground. This is a separate ground connection for the internal power devices. Connect to the application power ground plane.
17CBAn optional capacitor can be connected from this pin to SW1.
18, 19PVINPower input terminal for the power switching stage.

1.1 Package

Figure 1-1. Pin Configuration 20-Lead 5.8 mm x 4.9 mm LGA (Top View)