CTRLA

Control A

Name:: CTRLA
Offset:: 0x00
Reset:: 0x00
Access:: -

Bit7	6	5	4	3	2	1	0
	RUNSTDBY		SYNCUPD		CLKSEL[1:0]		ENABLE
Access	R/W		R/W		R/W	R/W	R/W
Reset	0		0		0	0	0

Bit 6 – RUNSTDBY: Run in Standby

Run in Standby

Writing a ‘1’ to this bit will enable the peripheral to run in Standby sleep mode. Not applicable when CLKSEL is set to 0x2 (CLK_TCA).

Bit 4 – SYNCUPD: Synchronize Update

Synchronize Update

When this bit is written to ‘1’, the TCB will restart whenever TCA0 is restarted or overflows. This can be used to synchronize capture with the PWM period. Not applicable when CLKSEL is set to 0x1 (CLK_PER/2).

Bits 2:1 – CLKSEL[1:0]: Clock Select

Clock Select

Writing these bits selects the clock source for this peripheral.

Value	Name	Description
`0x0`	CLKDIV1	CLK_PER
`0x1`	CLKDIV2	CLK_PER/DIV2
`0x3`	CLKTCA	Use TCA_CLK from TCA0
`0x4`	-	Reserved

Bit 0 – ENABLE: Enable

Enable

Writing this bit to ‘1’ enables the Timer/Counter type B peripheral.