Clock Generation

Figure 1. ADC Prescaler

The ADC requires an input clock frequency between 50 kHz and 1.5 MHz for maximum resolution. If a lower resolution than ten bits is selected, the input clock frequency to the ADC can be higher than 1.5 MHz to get a higher sample rate.

The ADC module contains a prescaler which generates the ADC clock (CLK_ADC) from the peripheral clock (CLK_PER) above 100 kHz. The prescaling is selected by writing to the Prescaler (PRESC) bit field in the Control C (ADCn.CTRLC) register. The prescaler starts counting from the moment the ADC is switched on by writing a ‘1’ to the ENABLE bit in the ADCn.CTRLA register. The prescaler keeps running as long as the ENABLE bit is ‘1’. The prescaler counter is reset to zero when the ENABLE bit is ‘0’.

When initiating a conversion by writing a ‘1’ to the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register or from an event, the conversion starts after one CLK_PER cycle. The prescaler is kept in Reset, as long as there is no ongoing conversion. This assures a fixed delay from the trigger to the actual start of conversion of a maximum of 2 CLK_PER cycles, as follows:

Figure 2. Start Conversion and Clock Generation