Sleep Mode Operation

The ADC is, by default, disabled in Standby sleep mode.

The ADC can stay fully operational in Standby sleep mode if the Run in Standby (RUNSTDBY) bit in the Control A (ADCn.CTRLA) register is written to ‘1’.

If the device is entering Standby sleep mode when RUNSTDBY is ‘1’, the ADC will stay active, hence any ongoing conversions will be completed, and interrupts will be executed as configured.

In Standby sleep mode, an ADC conversion must be triggered via the Event System (EVSYS), or the ADC must be in Free-Running mode with the first conversion triggered by software before entering a sleep mode. The peripheral clock is requested if needed and is turned off after the conversion is completed.

When an input event trigger occurs, the positive edge will be detected, the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register is set, and the conversion will start. When the conversion is completed, the Result Ready (RESRDY) flag in the Interrupt Flags (ADCn.INTFLAGS) register is set, and the STCONV bit in ADCn.COMMAND is cleared.

The reference source and supply infrastructure need time to stabilize when activated in Standby sleep mode. Configure a delay for the start of the first conversion by writing a non-zero value to the Initial Delay (INITDLY) bits in the Control D (ADCn.CTRLD) register.

In Power-Down sleep mode, no conversions are possible. Any ongoing conversions are halted and will be resumed when going out of a sleep mode. At the end of conversion, the Result Ready (RESRDY) flag will be set, but the content of the result (ADCn.RES) registers is invalid since the ADC was halted in the middle of a conversion.