UPDI Enable with High-Voltage Override of RESET Pin

GPIO or Reset functionality on the RESET pin can be overridden by the UPDI by using high-voltage (HV) programming. Applying an HV pulse to the RESET pin will switch the pin functionality to UPDI. This is independent of the RESET Pin Configuration (RSTPINCFG) in FUSE.SYSCFG0. Follow these steps to override the pin functionality:
  1. 1.Recommended: Reset the device before starting the HV enable sequence.
  2. 2.Apply the HV signal, as described in Figure 1.
  3. 3.Send the NVMPROG key using the key instruction after the first SYNC character to start programming. Locked devices will only accept the CHIPERASE key. See also section Chip Erase.
  4. 4.After the programming is finished, reset the UPDI by writing the UPDI Disable (UPDIDIS) bit in the Control B (UPDI.CTRLB) register to ‘1’ using the STCS instruction.

During power-up, the RESET signal must be released before the HV pulse can be applied. The duration of the pulse is recommended in the range from 100 μs to 1 ms before tri-stating.

When applying the rising edge of the HV pulse, the UPDI will be reset. After tri-stating, the UPDI will remain in Reset until the RESET pin is driven low by the debugger. This will release the UPDI Reset and initiate the same enable sequence, as explained in UPDI Enable with Fuse Override of RESET Pin.

Figure 1. UPDI Enable Sequence by High-Voltage (HV) Programming

When enabled by an HV pulse, only a POR will disable the UPDI configuration on the RESET pin and restore the default setting. If issuing a UPDI Disable command through the UPDIDIS bit in UPDI.CTRLB, the UPDI will be reset, and the clock request will be canceled, but the RESET pin will remain in UPDI configuration.

  1. 1.If insufficient external protection is added to the UPDI pin, an ESD pulse can be interpreted by the device as a high-voltage override and enable the UPDI.
  2. 2.The actual threshold voltage for the UPDI HV activation depends on VDD. See the Electrical Characteristics section for more details.